Digital Signal Processing (DSP)

DSP System Design and Verification

MATLAB, Simulink, and related signal processing products provide an integrated workflow for verifying, prototyping, and implementing audio, video, communications, radar, and other signal processing-intensive systems.

Develop Efficient Algorithms for Embedded DSP Systems

Algorithm development for embedded DSP systems involves transforming the high-level concept code into a version that uses a well-tuned set of low-level arithmetic and logical operations.

MathWorks products provide a direct path to implementation. You can perform bit-true simulations of your algorithm based on fixed-point representations of your data.  You can then compile your floating-point or fixed-point MATLAB algorithms into efficient and numerically reliable C code. As a result, you maintain a single design source and one development environment from concept to implementation.

Verify System Behavior Before Implementing on Hardware

Speed up system verification tasks by performing simulation and verification in a single environment. Create system-level test benches for your reference model and verify system behavior against requirements before implementing hardware and software.

You can integrate your system model into downstream design and verification workflows by connecting to popular third-party HDL and analog/mixed-signal simulators, embedded development tools, and development boards. Using the model as a reusable test bench, you can verify your implementation via cosimulation, processor-in-the-loop, and hardware-in-the-loop techniques.

Prototype and Test Your Design on Embedded Software or Hardware Targets

The same environment that you use for simulation and verification is used to develop a real-time implementation of your embedded signal processing system. You generate real-time C code from your system model and then download the generated code and executable onto a supported DSP board for real-time algorithm evaluation.

To implement your system design on a target FPGA or ASIC, you can generate bit-true, cycle-accurate HDL code from your model. The generated HDL code is synthesizable, and can be easily exported to synthesis and layout tools for hardware realization.