Fixed-Point Made Easy for RTL Implementation
| Start Time | End Time |
|---|---|
| 12 May 2026, 1:00 PM EDT | 12 May 2026, 2:00 PM EDT |
Overview
One of the biggest challenges in RTL implementation is the process of quantizing mathematical operations to fixed-point for more efficient implementation.
This session teaches the fundamentals of the fixed-point number system and fixed-point arithmetic, along with considerations for targeting ASIC as well as popular FPGA/SoC devices. These concepts are then reinforced through practical demonstrations, capped by walking through the process of quantizing a signal processing design.
Topics include:
- Fixed-point theory
- Fixed-point number system
- Mathematical range
- Quantization error in the time and frequency domains
- Common functions
- Arithmetic: square root, reciprocal, log2
- Trigonometry: cosine, sine, atan2
- Using native floating point for full-precision calculations
- Signal processing: FIR, FFT
- Example: LMS filter
- MATLAB golden reference
- ASIC implementation
- Targeting FPGA/SoC devices
- Establishing equivalence (bit exact and feedback)
About the Presenter
As a principal applications engineer, Jeff Miller has 20 years of experience supporting customers for adopting HDL code generation for communication systems. Customer projects have included HDL designs for high performance FFT, FIR, Matrix Mathematics, Encryption, Custom Floating Point, and 5G/WLAN/LTE receivers. Prior to joining MathWorks, Jeff worked at Applied Signal Technology doing signal intelligence, and at Morphics Technology doing commercial wireless communications. Jeff has a Master of Electrical Engineering from Georgia Tech and a Master of Education from the University of Arizona.
This event is part of a series of related topics. View the full list of events in this series.
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