ASML Develops Virtual Metrology Technology for Semiconductor Manufacturing with Machine Learning

In nanofabrication, photolithography is the fundamental patterning step that controls the size of a microchip. During photolithography, a low-wavelength power source is conditioned with optics through an image that is then reduced in size with more optics into a thin film of light-sensitive chemical covering a substrate, typically silicon. This step is repeated until all available surface area on the substrate has been exposed with the same image; the result is referred to as a layer. Multiple exposed layers are needed to create the complex microscopic structures that make up a chip. To prevent yield issues due to connection failures between layers, all patterns between layers must line up as intended.

To ensure layer alignment without affecting throughput, ASML’s TWINSCAN photolithography system must limit the number of alignment marks it measures before the exposure step. The general rule is that the time required to measure alignment marks cannot be longer than the time required to expose the previous wafer in the sequence. Due to the large quantity of overlay marks required for a proper overlay model correction, it is not feasible to measure every wafer coming out of a TWINSCAN system.

ASML used MATLAB^® and Statistics and Machine Learning Toolbox™ to develop virtual overlay metrology software. This software applies machine learning techniques to come up with a predicted estimate of overlay metrology for every wafer, using alignment metrology data.

“The work we’ve done with MATLAB and machine learning demonstrates industry leadership in the best use of existing metrology,” says Emil Schmitt-Weaver, applications development engineer at ASML. “The papers we’ve published on this work have attracted the interest of customers looking to improve their manufacturing processes with ASML products.”