CIC Decimation HDL Optimized

Decimate signal using cascaded integrator-comb filter optimized for HDL code generation

• Library:

• DSP System Toolbox HDL Support / Filtering

Description

The CIC Decimation HDL Optimized block decimates an input signal by using a cascaded integrator-comb (CIC) decimation filter. CIC filters are a class of linear phase FIR filters consisting of a comb part and an integrator part. The CIC decimation filter structure consists of N sections of cascaded integrators, a rate change factor of R, and then N sections of cascaded comb filters. For more information about CIC Decimation filter, see Algorithms.

The block supports fixed decimation rate. It provides an architecture suitable for HDL code generation and hardware deployment.

The block supports real and complex fixed-point inputs.

Ports

Input

data — Input data

scalar

Input data, specified as a signed integer or signed fixed point with word length less than or equal to 32.

Data Types: int8 | int16 | int32 | fixed point
Complex Number Support: Yes

valid — Indication of valid input data

Boolean scalar

Control signal that indicates if the input data is valid. When this value is 1 (true), the block captures the values from the data input port. When this value is 0 (false), the block ignores the values from the data input port.

Data Types: Boolean

reset — Clears internal states

Boolean scalar

Clears internal states, specified as a Boolean scalar.

When this value is 1 (true), the block stops the current calculation and clears all internal states. When the reset is 0 (false) and the input valid is 1 (true), the block starts a new filtering operation.

Dependencies

To enable this port, select the Enable reset input port parameter.

Data Types: Boolean

Output

data — Output data

scalar

CIC decimated output data, returned as a scalar.

You can define the output data type of the block. See Output data type.

Data Types: int8 | int16 | int32 | fixed point
Complex Number Support: Yes

valid — Indication of valid output data

Boolean scalar

Control signal that indicates if the data from the data output port is valid. When this value is 1 (true), the block returns valid data on the data output port. When this value is 0 (false), the values on the data output port are not valid.

Data Types: Boolean

Parameters

Decimation factor (R) — Decimation factor

2 (default) | integer from 2 to 2048

Specify the decimation factor rate with which you want to decimate the input as an integer from 2 to 2048.

Differential delay (M) — Differential delay

1 (default) | 2

Specify the differential delay of the comb part of the block as an integer from 1 to 2.

Number of sections (N) — Number of integrator and comb sections

2 (default) | integer from 1 to 6

Specify the number of sections in either the comb part or the integrator part of the block as an integer from 1 to 6.

Output data type — Data type of output

Full precision (default) | Same word length as input | Minimum section word lengths

Select the data type to represent the output data.

• Full precision — The output data type has a word length equal to the input word length plus gain bits.

• Same word length as input — The output data type has a word length equal to the input word length.

• Minimum section word lengths — The output data type uses the word length you specify in the Output word length parameter. When you select this parameter, the block applies the Pruning algorithm internally. For more information about Pruning algorithm, see [1].

Output word length — Word length of output

16 (default) | integer from 2 to 104

Word length of the output, specified as an integer from 2 to 104.

Note

When the Output word length value entered is in the range 2 to 6, there are chances of output data getting overflowed.

Dependencies

To enable this parameter, set the Output data type parameter to Minimum section word lengths.

Enable reset input port — Reset signal

off (default) | on

Select this parameter to enable the reset input port.

Model Examples

Implement CIC Decimation Filter for HDL

Use the CIC Decimation HDL Optimized block to filter and downsample data. The example performs these steps:

Open Script

Algorithms

CIC Decimation Filter

The transfer function of a CIC decimation filter is

$$H(z)={\left[{\displaystyle \sum _{k=0}^{RM-1}{z}^{-k}}\right]}^N=\frac{{\left(1-z^{-RM}\right)}^N}{{\left(1-z^{-1}\right)}^N}=\frac{1}{{\left(1-z^{-1}\right)}^N}·\frac{{\left(1-z^{-RM}\right)}^N}{1}=H_{\text{I}}{}^N(z)·H_{\text{c}}{}^N(z),$$

where:

• H_I is the transfer function of the integrator part of the filter.

• H_C is the transfer function of the comb part of the filter.

• N is the number of sections. The number of sections in a CIC filter is defined as the number of sections in either the comb part or the integrator part of the filter. This value does not represent the total number of sections throughout the entire filter.

• R is the decimation factor.

• M is the differential delay.

CIC Filter Structure

The CIC Decimation HDL Optimized block has the CIC filter structure shown in this figure. The structure consists of N sections of cascaded integrators, a rate change factor of R, followed by N sections of cascaded comb filters [1].

The unit delay in the integrator part of the CIC Filter can be located in either the feed-forward or feedback path. These two configurations yield an identical filter frequency response. However, the numerical outputs from these two configurations are different due to the latency. This block puts the unit delay in the feed-forward path of the integrator, because the configuration is preferred for HDL implementation.

Fixed Decimation

The block downsamples the integrator stage output using R, a fixed decimation rate provided by using the Decimation factor (R) parameter. At the downsampler stage, the block uses a counter to count the valid input samples, which depend on the decimation rate. The block provides the decimated output to the comb part.

Output Data Type

This section explains how the block outputs based on the output data type selection. Let us take an example, a block with R, M, and N values 8, 1, and 3, respectively, with an input width 16. The output word length is calculated as: ,

where:

• 

• B_IN is the input word length.

• B_OUT is the output word length.

When you set the Output data type parameter to Full precision, the block outputs data with a word length 25 by adding nine gain bits to the input word length 16.

When you set the Output data type parameter to Same word length as input, the block outputs data with a word length 16, which is same as the input word length 16. The internal integrator and comb stages still use the full-precision data type with 25 bits.

When you set the Output data type parameter to Minimum section word lengths and the Output word length to 16, the block outputs data with word length 16, by changing the bit width at each stage, based on the pruning algorithm.

If the Output word length is lesser than the number of bits required at the block output, the least significant bit (LSB)s at the earlier stages are pruned. The number of LSBs to discard at each stage is provided in the Hogenauer algorithm [1]. This algorithm minimizes the loss of information in the output data.

Latency

This figure shows the output and latency of the block for the default configuration, that is, fixed decimation rate with R, M, and N values 2, 1, and 2, respectively. The block returns valid output data at every second cycle based on the fixed Decimation factor (R) value of 2. The latency of the block is 5 clock cycles, calculated as 3 + N.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. This table shows the resource and performance data synthesis results of the block with the default configuration at fixed decimation rate. In the default configuration, R, M, and N values are 2, 1, and 2, respectively. The generated HDL is targeted to Xilinx^® Zynq^® XC7Z045-FFG900-2 FPGA. The design achieves a clock frequency of 700.77 MHz.

Resource	Number Used
LUTs	96
Registers	166

The resources and frequencies vary based on the R, M, and N values and other parameter values selected in the block mask.

References

[1] Hogenauer, E.B. “An Economical Class of Digital Filters for Decimation and Interpolation.” IEEE Transactions on Acoustics, Speech and Signal Processing. Vol. 29, Number 2, 1981, pp. 155–162.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).