CIC Decimation HDL Optimized

Decimate signal using cascaded integrator-comb filter optimized for HDL code generation

• Library:

• DSP System Toolbox HDL Support / Filtering

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Description

The CIC Decimation HDL Optimized block decimates an input signal by using a cascaded integrator-comb (CIC) decimation filter. CIC decimation filters are a class of linear phase FIR filters consisting of a comb part and an integrator part. The CIC decimation filter structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters. For more information about CIC decimation filters, see Algorithms.

The block supports scalar and vector inputs. For both types of inputs, the block provides a scalar output. The block supports fixed and variable decimation for scalar inputs and only fixed decimation for vector inputs.

The block provides an architecture suitable for HDL code generation and hardware deployment.

Ports

Input

data — Input data

scalar | column vector

Specify input data as a scalar or a column vector of length 1 to 64. The input data must be a signed integer or signed fixed point with a word length less than or equal to 32. Decimation factor (R) parameter must be an integer multiple of the input frame size.

Data Types: int8 | int16 | int32 | fixed point
Complex Number Support: Yes

valid — Indication of valid input data

scalar

This port is a control signal that indicates if the input data is valid. When this value is 1, the block captures the values from the data input port. When this value is 0, the block ignores the values from the data input port.

Data Types: Boolean

decimFactor — Variable decimation rate

scalar

Use this port to dynamically specify the variable decimation rate during run time.

This value must be of data type ufix12 and an integer in the range from 2 to the Decimation factor (R) parameter value.

Dependencies

To enable this port, select the Variable decimation parameter.

Data Types: fixdt(0,12,0)

reset — Clear internal states

scalar

When this value is 1, the block stops the current calculation and clears all internal states. When this value is 0 and the input valid port is 1, the block starts a new filtering operation.

Dependencies

To enable this port, select the Enable reset input port parameter.

Data Types: Boolean

Output

data — CIC-decimated output data

scalar

You can define the data type of this output by setting the Output data type parameter.

Data Types: int8 | int16 | int32 | fixed point
Complex Number Support: Yes

valid — Indication of valid output data

scalar

This port is a control signal that indicates if the data from the data output port is valid. When this value is 1, the block returns valid data on the data output port. When this value is 0, the values on the data output port are not valid.

Data Types: Boolean

Parameters

Variable decimation — Variable decimation rate

off (default) | on

• Select this parameter to operate the block with a variable decimation rate specified from the decimFactor input port.

• Clear this parameter to operate the block with a fixed decimation rate specified from the Decimation factor (R) parameter.

Note

For vector inputs, the block does not support variable decimation.

Decimation factor (R) — Decimation factor

2 (default) | integer from 2 to 2048

Specify the decimation factor rate with which you want to decimate the input.

When you select the Variable decimation parameter, the Decimation factor (R) parameter sets the upper bound of the range of valid values for the decimFactor input port.

Differential delay (M) — Differential delay

1 (default) | 2

Specify the differential delay of the comb part of the block.

Number of sections (N) — Number of integrator and comb sections

2 (default) | 1 | 3 | 4 | 5 | 6

Specify the number of sections in either the comb part or the integrator part of the block.

Output data type — Data type of output

Full precision (default) | Same word length as input | Minimum section word lengths

Select the data type for the output data.

• Full precision — The output data type has a word length equal to the input word length plus gain bits.

• Same word length as input — The output data type has a word length equal to the input word length.

• Minimum section word lengths — The output data type uses the word length you specify in the Output word length parameter. When you select this option, the block applies the Pruning algorithm. For more information about the Pruning algorithm, see [1]. This option is not supported when you select the Variable decimation parameter.

Output word length — Word length of output

16 (default) | integer from 2 to 104

Specify the word length of the output.

Note

When this value is 2, 3, 4, 5, or 6, the block might overflow the output data.

Dependencies

To enable this parameter, set the Output data type parameter to Minimum section word lengths.

Gain correction — Output gain compensation

off (default) | on

Select this parameter to compensate for the output gain of the block.

Depending on the type of input, the decimation you specify, and the value of this parameter, the latency of the block changes. Here, N means the number of sections and vecLen means the length of the vector.

For a scalar input with fixed decimation (the Variable decimation parameter is cleared):

• When you clear this parameter, the latency of the block is 3 + N clock cycles.

• When you select this parameter, the latency of the block is 3 + N + 9 clock cycles.

For a scalar input with variable decimation (the Variable decimation parameter is selected):

• When you clear this parameter, the latency of the block is 4 + N clock cycles.

• When you select this parameter, the latency of the block is 4 + N + 9 clock cycles.

For a vector input with fixed decimation (the Variable decimation parameter is cleared):

• When you clear this parameter, the latency of the block is floor((vecLen – 1) * (N/vecLen)) + 1 + N + (2 + (vecLen + 1) * N clock cycles.

• When you select this parameter, the latency of the block is floor((vecLen – 1) * (N/vecLen)) + 1 + N + (2 + (vecLen + 1) * N) + 9 clock cycles.

Note

For vector inputs, the block does not support variable decimation.

Enable reset input port — Reset signal

off (default) | on

Select this parameter to enable the reset input port.

Model Examples

Implement CIC Decimation Filter for HDL

Use the CIC Decimation HDL Optimized block to filter and downsample data. You can generate HDL code from the subsystem in the Simulink(R)model.

HDL Implementation of a Digital Down-Converter for LTE

Design a digital down-converter (DDC) for radio communication applications such as LTE, and generate HDL code with HDL Coder™.

Algorithms

CIC Decimation Filter

The transfer function of a CIC decimation filter is

$$H(z)={\left[{\displaystyle \sum _{k=0}^{RM-1}{z}^{-k}}\right]}^N=\frac{{\left(1-z^{-RM}\right)}^N}{{\left(1-z^{-1}\right)}^N}=\frac{1}{{\left(1-z^{-1}\right)}^N}·\frac{{\left(1-z^{-RM}\right)}^N}{1}=H_{\text{I}}{}^N(z)·H_{\text{c}}{}^N(z),$$

where:

• H_I is the transfer function of the integrator part of the CIC filter.

• H_C is the transfer function of the comb part of the CIC filter.

• N is the number of sections. The number of sections in a CIC filter is defined as the number of sections in either the comb part or integrator part of the filter. This value does not represent the total number of sections throughout the entire filter.

• R is the decimation factor.

• M is the differential delay.

CIC Filter Structure

The CIC Decimation HDL Optimized block has the CIC filter structure shown in this figure. The structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters [1].

You can locate the unit delay in the integrator part of the CIC filter in either the feed-forward or feedback path. These two configurations yield an identical filter frequency response. However, the numerical outputs from these two configurations are different due to the latency of the block. Because this configuration is preferred for HDL implementation, this block puts the unit delay in the feed-forward path of the integrator.

Fixed and Variable Decimation

The block downsamples the integrator stage output using R, either the fixed decimation rate provided using the Decimation factor (R) parameter or the variable decimation rate provided using the decimFactor input port. At the downsampler stage, the block uses a counter to count the valid input samples, which depend on the decimation rate. Whenever the decimation rate changes, the block resets and starts a new calculation from the next sample. This mechanism prevents the block from accumulating false values. Then, the block provides the decimated output to the comb part of the CIC filter.

Gain Correction

The gain of the block is given by $$Gain={(R\text{x}M)}^N$$, where:

• R is the Decimation factor (R) parameter value.

• M is the Differential delay (M) parameter value.

• N is the Number of sections (N) parameter value.

The block implements gain correction in two parts: coarse gain and fine gain. In coarse gain correction, the block calculates the shift value, adds the shift value to the fractional bits to create a numeric type, and performs a bit-shift left and reinterpretcast. In fine gain correction, the block divides the remaining gain with the coarse gain if the gain is not a power of 2. Then, the block multiplies the corrected coarse gain corrected value with the inverse value of the fine gain. Before the block starts processing, all possible shift and fine gain values are precalculated initially and stored in an array.

You can modify this equation as $$Gain=2^{cGain}\text{x}fGain$$. In this equation, cGain is the coarse gain, and fGain is the fine gain. These gains are given by these equations.

• $$cGain=floor({\log }_{2}Gain)$$

• $$fGain=Gain/2^{cGain}=Gain\text{x}{2}^{-cGain}{}^{}$$

To perform gain correction when the Variable decimation parameter is selected, the block sets the output data type configured with the maximum decimation rate and bit-shifts left for all of the values under the maximum decimation rate. The bit-shift value is equal to $${\text{Maximum gain - log}}_{\text{2}}\text{(current gain)}$$.

Output Data Type

How the block outputs data is based on the output data type selection. Consider a block with R, M, and N values of 8, 1, and 3, respectively, and an input width of 16. The output word length is calculated as $$B_{\text{OUT}}=B_{\text{IN}}+[{\log }_2(Gain)]$$,

where:

• $$Gain={(R\text{x}M)}^N$$

• B_IN is the input word length.

• B_OUT is the output word length.

When you set the Output data type parameter to Full precision, the block outputs data with a word length of 25 by adding nine gain bits to the input word length of 16.

When you set the Output data type parameter to Same word length as input, the block outputs data with a word length of 16, which is the same length as the input word length. The internal integrator and comb stages use the full-precision data type with 25 bits.

When you set the Output data type parameter to Minimum section word lengths and the Output word length parameter to 16, the block outputs data with a word length of 16. In this case, the block changes the bit width at each stage, based on the Pruning algorithm.

If the Output word length parameter value is less than the number of bits required at the block output, the least significant bits (LSBs) at the earlier stages are pruned. The Hogenauer algorithm [1] provides the number of LSBs to discard at each stage. This algorithm minimizes the loss of information in the output data.

Latency

This section shows the latencies of the block for a scalar input when the block is operated with fixed and variable decimation rates and for a vector input when the block is operated with a fixed decimation rate.

Scalar Input

This section shows the output of the block for a scalar input with different R, M, and N values.

This figure shows the output of the block for the default configuration (that is, with a fixed decimation rate and R, M, and N values of 2, 1, and 2, respectively). The block returns valid output data at every second cycle based on the fixed Decimation factor (R) parameter value of 2. The latency of the block is 5 clock cycles and is calculated as 3 + N, where N is the number of sections.

This figure shows the output of the block with a fixed decimation rate, R, M, and N values of 8, 1, and 3, respectively, and the Gain correction parameter selected. The block returns valid output data at every eighth cycle based on the fixed Decimation factor (R) parameter value of 8. The latency of the block is 15 clock cycles, and is calculated as 3 + N + 9, where N is the number of sections.

This figure shows the output of the block with variable decimation rate (decimFactor input port) values 2, 4, and 8 and for M and N values of 1 and 3, respectively. In this case, the Gain correction parameter is cleared. The block returns valid output data at the second, fourth, and eighth cycles corresponding to the decimFactor port values 2, 4, and 8, respectively. The block accepts decimFactor port value changes only when the valid input port is 1. The latency of the block is 7 clock cycles and is calculated as 4 + N, where N is the number of sections.

Vector Input

The latency of the block for a vector input is calculated using this formula: floor((vecLen – 1) * (N/vecLen)) + 1 + N + 9 * Gain correction + (2 + (vecLen + 1) * N), where vecLen is the length of the vector and N is the number of sections.

This figure shows the output of the block for a two-element column vector input with the default configuration, (that is, with a fixed decimation rate and R, M, and N values of 2, 1, and 2, respectively). The latency of the block is 12 clock cycles.

This figure shows the output of the block for an eight-element column vector input with a fixed decimation rate, R, M, and N values of 8, 1, and 3, respectively, and the Gain correction parameter selected. The latency of the block is 44 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. This table shows the resource and performance data synthesis results of the block for a scalar input with fixed and variable decimation rates and for a two-element column vector input with a fixed decimation rate when R, M, and N are 2, 1, and 2, respectively. The generated HDL is targeted to the Xilinx^® Zynq^®- 7000 ZC706 evaluation board.

Input Data	Decimation Type	Slice LUTs	Slice Registers	Maximum Frequency in MHz
Scalar	Fixed rate	101	166	711.74
	Variable rate	206	186	441.70
Vector	Fixed rate	218	627	624.61

The resources and frequencies vary based on the type of input data, R, M, and N values, and other parameter values selected in the block mask. Using a vector input can increase the throughput, however this option also increases the number of hardware resources that the block uses.

References

[1] Hogenauer, E. “An Economical Class of Digital Filters for Decimation and Interpolation.” IEEE Transactions on Acoustics, Speech, and Signal Processing 29, no. 2 (April 1981): 155–62. https://doi.org/10.1109/TASSP.1981.1163535.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).