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Minimize clock enables

Minimize clock enable logic

Model Configuration Pane: Global Settings / Ports

Description

Omit generation of clock enable logic for single-rate designs.

Dependencies

This option is ignored, when the HDL Coding Standard is set to Industry.

Settings

off (default) | on

Default: Off

on

For single-rate models, omit generation of clock enable logic wherever possible. The following VHDL® code example does not define or examine a clock enable signal. When the clock signal (clk) goes high, the current signal value is output.

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      Unit_Delay_out1 <= In1_signed;
    END IF;
  END PROCESS Unit_Delay_process;
off

Generate clock enable logic. The following VHDL code extract represents a register with a clock enable (enb)

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        Unit_Delay_out1 <= In1_signed;
      END IF;
    END IF;
  END PROCESS Unit_Delay_process;

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to minimize Clock Enable signals when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        'MinimizeClockEnables','on')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MinimizeClockEnables','on')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: MinimizeClockEnables
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Exceptions

In some cases, HDL Coder™ emits clock enables even when Minimize clock enables is selected. These cases are:

  • Registers inside Enabled, State-Enabled, and Triggered subsystems.

  • Multirate models.

  • The coder always emits clock enables for the following blocks:

    • commseqgen2/PN Sequence Generator

    • dspsigops/NCO

      Note

      HDL support for the NCO block will be removed in a future release. Use the NCO HDL Optimized block instead.

    • dspsrcs4/Sine Wave

    • hdldemolib/HDL FFT

    • built-in/DiscreteFir

    • dspmlti4/CIC Decimation

    • dspmlti4/CIC Interpolation

    • dspmlti4/FIR Decimation

    • dspmlti4/FIR Interpolation

    • dspadpt3/LMS Filter

    • dsparch4/Biquad Filter

Note

If your design uses a RAM block such as a Dual Rate Dual Port RAM with the RAM Architecture set to Generic RAM without Clock Enable, the code generator ignores the Minimize clock enables setting.

Version History

Introduced in R2012b