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Timing controller architecture

Architecture of generated timing controller

Model Configuration Pane: Global Settings / Coding style

Description

Specify the architecture of the generated timing controller. HDL Coder™ generates a timing controller in the DUT if this parameter is set to default or resettable and a timing controller is required by the design. For example, a timing controller is required by the design when:

  • You generate HDL code for a multirate model.

  • You specify a cascade block implementation for certain blocks.

HDL Coder generates a separate timing controller code file that contains a module that defines timing signals, such as clock, reset, external clock enable inputs and clock enable output. In a multirate model, the timing controller module generates the required rates from a single primary clock using one or more counters and multiple clock enables. For more information, see Timing Controller for Multirate Models.

Settings

default (default) | resettable | external

Default: default

default

Generate a timing controller in the DUT without a reset. This setting generates a timing controller code file as its own HDL file and instantiates the timing controller in the DUT at the top level.

resettable

Generate a timing controller in the DUT with a reset port. This setting generates a timing controller code file as its own HDL file and instantiates the timing controller in the DUT at the top level. If you select this option, the Clock inputs value must be Single.

external

Move the timing controller externally and expose the clock enable signals from the top-level design. This setting prevents the creation of a timing controller inside the DUT and does not generate a timing controller code file during HDL code generation, which allows you to integrate your own custom external timing controller into the design. If you select this option, the Clock inputs value must be Single.

Note

When generating a test bench to validate your design, a timing controller file is generated to drive the DUT timing controller inputs for test bench validation. HDL Coder still keeps the clock enable signals exposed at the top-level design for external timing controller integration.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: TimingControllerArch
Type: character vector
Value:'default' | 'resettable' | 'external'
Default: 'default'

Version History

Introduced in R2014a

See Also