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Introduction to Stateflow HDL Code Generation

Stateflow® charts provide concise descriptions of complex system behavior by using hierarchical finite state machine (FSM) theory, flow diagram notation, and state-transition diagrams.

You use a chart to model a finite state machine or a complex control algorithm intended for realization as an ASIC or FPGA. When the model meets design requirements, you then generate HDL code (VHDL®, Verilog® or SystemVerilog) that implements the design embodied in the model. You can simulate and synthesize generated HDL code by using industry standard tools, and then map your system designs into FPGAs and ASICs. For more information on how to generate HDL code for finite state machines, see Generate HDL for Mealy and Moore Finite State Machines.

Generation of VHDL, Verilog or SystemVerilog code from a model containing a chart does not differ greatly from HDL code generation from other models. The HDL code generator is designed to:

  • Support the largest possible subset of chart semantics consistent with HDL code. This broad subset means that you can generate HDL code from existing models without significant remodeling.

  • Generate bit-true, cycle-accurate HDL code that is fully compatible with Stateflow simulation semantics.


Using the hdlcodercfir model, the example shows how to generate HDL code for a subsystem that includes Stateflow charts.

To open the model, at the command line, enter:


Chart Initialization

Enabling the Execute (enter) Chart at Initialization property executes the update chart function immediately following chart initialization. You can keep the chart property Execute (enter) Chart at Initialization disabled. This property can significantly alter the Stateflow Chart behavior and the generated HDL Code. Execution of a Chart at Initialization (Stateflow) describes the effect of this property on a Stateflow Chart.

You cannot perform arithmetic in initialization actions because reset actions cannot handle the delay of combinatorial logic.

You can select or clear Initialize Outputs Every Time Chart Wakes Up. If you clear it, the generated HDL code includes an additional register for the state machine output values.

Tunable Parameters

You can use a tunable parameter in a Stateflow Chart intended for HDL code generation.

For more information, see Generate DUT Ports for Tunable Parameters.

Comments in Stateflow Charts

When your Simulink® model contains a Stateflow Chart that uses comments, HDL Coder™ generates the comments in the HDL code.

When you generate Verilog code from the model, HDL Coder displays the comments in the Stateflow Chart inline beside the corresponding Stateflow object.


HDL Coder does not support Stateflow blocks that contain messages for HDL code generation.

Location of Charts in the Model

A chart intended for HDL code generation must be part of a Simulink subsystem. If the chart for which you want to generate code is at the root level of your model, embed the chart in a subsystem. Connect the relevant signals to the subsystem inputs and outputs.

Data Types

The code generator supports a subset of MATLAB® data types in charts that include:

  • Signed and unsigned integer

  • Fixed point

  • Boolean

  • Enumeration


Except for data types assigned to ports, multidimensional arrays of these types are supported. Port data types must be either scalar or vector.

If you use single and double data types, HDL Coder generates real data types in the HDL code. You can simulate and verify the code by using third-party simulators such as ModelSim®.

Real types are not synthesizable on the target FPGA device. The code generator does not support generation of HDL code for the Stateflow Chart in Native Floating Point mode. To generate synthesizable HDL code when you use floating-point data types, develop an algorithm by using MATLAB Function blocks or other Simulink Blocks Supported by Using Native Floating Point.

Imported Code

A chart intended for HDL code generation must be entirely self-contained. These restrictions apply:

  • Do not call MATLAB functions other than min or max.

  • Do not use MATLAB System objects in a Chart block.

  • Do not use MATLAB workspace data.

  • Do not call C math functions. HDL does not have a counterpart to the C math library.

  • If the Enable C-bit operations property is disabled, do not use the exponentiation operator (^). The exponentiation operator is implemented with the C Math Library function pow.

  • Do not include custom code. Information entered on the Simulation Target > Custom Code pane in the Configuration Parameters dialog box is ignored.

  • Do not share data (through Data Store Memory blocks) between charts. HDL Coder does not map such global data to HDL because HDL does not support global data.

Vector of Tunable Parameters

Vector of Tunable Parameters as data types for Chart blocks is not supported.

Input and Output Events

HDL Coder supports the use of input and output events with Stateflow charts, subject to these constraints:

  • You can define and use only one input event per Stateflow chart. There is no restriction on the number of output events that you can use.

  • The coder does not support HDL code generation for charts that have a single input event, and which also have nonzero initial values on the chart's output ports.

  • All input and output events must be edge-triggered.

For detailed information on input and output events, see Activate a Stateflow Chart by Sending Input Events (Stateflow) and Activate a Simulink Block by Sending Output Events (Stateflow).


Stateflow messages are not supported for HDL code generation.


Other than for loops, do not explicitly use loops in a chart intended for HDL code generation. Observe the following restrictions on for loops:

  • The data type of the loop counter variable must be int32.

  • HDL Coder supports only constant-bounded loops.

The for loop example, sf_for, shows a design pattern for a for loop that uses a graphical function.

Additional Restrictions

HDL Coder imposes additional restrictions on the use of classic chart features. These limitations exist because HDL does not support some features of general-purpose sequential programming languages.

  • Make separate copies for each instance of each atomic subchart. HDL Coder does not support code generation for atomic subcharts. For more information, see Convert an Atomic Subchart to a Normal Subchart (Stateflow).

  • Do not generate HDL code for Simulink Function block.

  • Do not define local events in a chart from which HDL code is generated.

    Do not use these implicit events:

    • enter

    • exit

    • change

    You can use these implicit events:

    • wakeup

    • tick

    If the base events are limited to these types of implicit events, you can use temporal logic.

  • Do not use recursion through graphical functions. HDL Coder does not support recursion.

  • Avoid unstructured code. Although charts allow unstructured code through transition flow diagrams and graphical functions, this usage results in goto statements and multiple function return statements. HDL does not support either goto statements or multiple function return statements. Therefore, do not use unstructured flow diagrams.

  • If you have not selected the Initialize Outputs Every Time Chart Wakes Up chart option, do not read from output ports.

  • Do not use Data Store Memory objects.

  • Do not use pointer (&) or indirection (*) operators. See Pointer and Address Operations (Stateflow).

  • If a chart gets a run-time overflow error during simulation, it is possible to disable data range error checking and generate HDL code for the chart. In such cases, some results obtained from the generated HDL code might not be bit-true to results from the simulation. The recommended practice is to enable overflow checking and eliminate overflow conditions from the model during simulation.

See Also

(Stateflow) | (Stateflow) | (Stateflow)

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