RAM Mapping Parameters

This page describes configuration parameters that reside in the HDL Code Generation > Optimization > General tab of the Configuration Parameters dialog box. Using the parameters in this section, you can reduce the area usage on the target device by trading-off block RAMs for registers. The parameters specify whether you want to map pipeline registers in the generated code to RAM, and the minimum RAM size for mapping to block RAMs on the FPGA.

Map pipeline delays to RAM

Map pipeline registers in the generated HDL code to RAM. Certain speed or area optimizations such as pipelining and resource sharing, or certain block implementations that you specify can insert pipeline registers in the generated HDL code. You can save area on the target device by mapping these pipeline registers to RAM.

Settings

Default: Off

On: Map pipeline registers in the generated HDL code to RAM. To map these registers to block RAMs, the RAM size must be greater than or equal to the RAM mapping threshold in bits. RAM size is the product Delay length * Word length * Vector length * Complex length.
Off: Do not map pipeline registers in the generated HDL code to RAM.

Command-Line Information

Property: MapPipelineDelaysToRAM

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can enable the MapPipelineDelaysToRAM setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'MapPipelineDelaysToRAM','on')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','MapPipelineDelaysToRAM','on')
makehdl('sfir_fixed/symmetric_fir')
```

RAM mapping threshold (bits)

Specify the minimum RAM size in bits for mapping to block RAMs. The code generator determines whether to use registers or RAM resources on the FPGA by comparing the RAM size of your design with the RAM mapping threshold that you specify.

Settings

Default: 256

The RAM mapping threshold must be an integer greater than or equal to zero. HDL Coder™ uses the threshold to determine whether or not to map the following elements to block RAMs instead of to registers:

Delay blocks
Persistent arrays in MATLAB Function blocks

Command-Line Information

Property: RAMMappingThreshold

Type: integer

Value: integer greater than or equal to 0

Default: 256

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can set the RAMMappingThreshold to 1024 when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

Pass the property as an argument to the makehdl function.

makehdl('sfir_fixed/symmetric_fir', ... 
        'RAMMappingThreshold','1024')

When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param('sfir_fixed','RAMMappingThreshold','1024')
makehdl('sfir_fixed/symmetric_fir')
```