A generated EDA script consists of three sections, generated and executed in the following order:
An initialization (
Init phase performs the required setup actions,
such as creating a design library or a project file. Some arguments
Init phase are implicit, for example, the
top-level entity or module name.
A command-per-file phase (
This phase of the script is called iteratively, once per generated
HDL file or once per signal. On each call, a different file or signal
name is passed in.
A termination phase (
is the final execution phase of the script. One application of this
phase is to execute a simulation of HDL code that was compiled in
Cmd phase. The
does not take arguments.
The HDL Coder™ software generates scripts by passing format
strings to the
fprintf function. Using the GUI
summarized in the following sections, you can pass in customized format
names to the script generator. Some of these format names take arguments,
such as the top-level entity or module name, or the names of the VHDL® or Verilog® files
in the design.
You can use valid
fprintf formatting characters.
'\n' inserts a newline into the script