50x PLL Frequency Synthesizer Behavior Study and Measurements

This example uses:

This example shows different measurements and scopes available to study the behavior of a PLL (phase-locked loop). In this example, the 1 MHz reference frequency of the PLL is multiplied by an integer (50).This drives to VCO output to 50 MHz.

model = 'MSPLL50x';
load_system(model);
sim(model);

riseFallSpec = 
  Group with properties:

              Name: 'RiseFallBox'
            Prompt: 'Rise/Fall Time'
               Row: 'new'
           Enabled: 'off'
           Visible: 'off'
      AlignPrompts: 'off'
    DialogControls: [1x7 Simulink.dialog.Control]
           Tooltip: ''

riseFallSpec = 
  Group with properties:

              Name: 'RiseFallBox'
            Prompt: 'Rise/Fall Time'
               Row: 'new'
           Enabled: 'off'
           Visible: 'off'
      AlignPrompts: 'off'
    DialogControls: [1x7 Simulink.dialog.Control]
           Tooltip: ''

riseFallSpec = 
  Group with properties:

              Name: 'RiseFallBox'
            Prompt: 'Rise/Fall Time'
               Row: 'new'
           Enabled: 'off'
           Visible: 'off'
      AlignPrompts: 'off'
    DialogControls: [1x7 Simulink.dialog.Control]
           Tooltip: ''

PLL Model Architecture

The PLL is relatively simple and consists of:

Ideal clock reference modeled with a sinusoidal signal source operating at 1 MHz.
Phase and Frequency detector block from Mixed-Signal Blockset™
Charge pump and loop compensator filter modeled with Simscape components and includes an additional Butterworth 3rd-order filter realized via its transfer function.
Voltage Controlled Oscillator block including phase noise from Mixed-Signal Blockset™.
Feedback divider from Mixed-Signal Blockest™ with factor equal to 50 to generate a PLL output of 50 MHz.

The purple areas in the Simulink model highlight the three different sets of measurements being made on the various signals generated within the PLL architecture.

Control Voltage Measurements

The input of the VCO is the control voltage generated by the loop filter. You can view the time dependent voltage signal on the time scope called 'VCO Control'.

The lock time is approximately around 200 μs.

You can also view this same signal in the frequency-domain by using the spectrum analyzer 'Baseband Spectrum Analyzer with Image Reject'. As the VCO signal is continuous time, this block applies a suitable anti-aliasing filter and resamples the signal at a fixed rate. The anti-aliasing filter bandwidth as well as the resampling frequency are determined by the mask parameter Visualization Bandwidth.

load_system([model '/Baseband Spectrum Analyzer with Image Reject']);
open_system([model '/Baseband Spectrum Analyzer with Image Reject'],'force');

You can view the instantaneous frequency error value of the control voltage by simply scaling the signal with the VCO sensitivity and comparing this quantity to the nominal frequency value of 1 MHz.

VCO Measurements

The output of the VCO is the PLL synthesized frequency. The voltage response is displayed on the time scope 'VCO Out'.

You can also observe the frequency response of the VCO by using the spectrum analyser 'RF Spectrum Analyzer with Image Reject'. As the VCO output signal is continuous time, this block applies a suitable anti-aliasing filter and resamples the signal at a fixed rate. The anti-aliasing filter bandwidth as well as the resampling frequency are determined by the mask parameter Visualization Bandwidth. To speed up the signal visualization, the signal is down-converted to baseband using a quadrature demodulator which has a local oscillator frequency specified by the parameter Center Frequency.

In the RF spectrum you can clearly see the effects of the VCO phase noise.

load_system([model '/RF Spectrum Analyzer with Image Reject']);
open_system([model '/RF Spectrum Analyzer with Image Reject'],'force');

Jitter Measurements

You can measure the aperture jitter properties of the generated clock. The jitter measurement block from the Mixed-Signal Blockset™ library provides cycle-to-cycle RMS jitter measurements.

After running the simulation for 1 ms, the aperture jitter measurement settles to the approximate value of 4.5 ns.

Additional Measurements

You can use the Mixed-Signal Blockset™ PLL measurement to verify the PLL performance. In this PLL model you find the measurement testbench (highlighted in purple) configured to measure lock time, lock frequency, and phase noise profile.

model = 'MSPLL50x_Testbench';
load_system(model);
sim(model);

At the end of the simulation, the mask of the testbench block (highlighted in purple) displays the requested information. You can also plot the phase noise profile to a separate figure.

Additional Information

In order to achieve optimal simulation speed and accuracy, change the default solver settings. This model uses ode113 solver and normal simulation mode. You can close the scope to further decrease the model execution time.

myConfigObj = getActiveConfigSet(model);
openDialog(myConfigObj)

You can inspect the solver settings in the Model Configuration Parameters for more details.