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Implements a phasor measurement unit using a phase-locked loop

**Library:**Simscape / Electrical / Specialized Power Systems / Fundamental Blocks / Measurements / Additional Measurements

Simscape / Electrical / Specialized Power Systems / Control & Measurements / Measurements

The PMU (PLL-Based, Positive-Sequence) block implements a phasor
measurement unit (PMU) using a phase-locked loop (PLL), which computes the
positive-sequence component of the input *abc* signal over a running
window of one cycle of fundamental frequency given by input *abc*. The
signal can be a set of three balanced or unbalanced signals which may contain harmonics.
The PMU (PLL-Based, Positive-Sequence) block is inspired by the IEEE Std
C37.118.1-2011.

The PLL (3ph) block tracks the frequency and phase of a sinusoidal
three-phase signal (*abc*) by using an internal frequency oscillator.
The control system adjusts the internal oscillator frequency to keep the phase
difference at `0`

.

The Positive-Sequence (PLL-Driven) block computes the positive-sequence
components (magnitude and phase) of a sinusoidal three-phase input signal
(*abc*) over a running window of one cycle of the fundamental
frequency tracked by the PLL (3ph) closed-loop control system. The reference frame
required for the computation is given by the angle (rad, varying between 0 and 2*pi),
synchronized on zero crossings of the fundamental (positive-sequence) of phase A. The
angle is also tracked by the PLL (3ph) closed-loop control system.

Because the block uses a running average window to perform the Fourier analysis, one
cycle of simulation must complete before the outputs give the correct magnitude and
angle. For example, the block response to a step change in the positive-sequence
component of a three-phase signal is a *one-cycle ramp*. For the
first cycle of simulation, the output is held constant at the values specified by the
initial input parameters.

The three outputs of the PMU (PLL-Based, Positive-Sequence) block
return the magnitude (same units as the input signal), the phase (in degrees relative to
the PLL phase), and the frequency of the positive-sequence component of the
*abc* input at the fundamental frequency, respectively.

The sample time (*Ts*) of the block, in seconds, is a function of the
nominal frequency *fn* and the sampling rate
*Nsr*.

Finally, the reporting rate (*Rt*), that determines the length of the
interval over which an event will be reported, is related to the sample time using a
reporting rate factor *k*, as follows:

*Rt* = *k* ×
*Ts*

Under subsynchronous conditions, the phasor estimation may present erroneous results.

Time synchronization from the common time source of a global positioning systems (GPS) radio clock is implicit in the model.

[1] *IEEE Standard for Synchrophasor Measurements for Power
Systems*. IEEE Std C37.118.1-2011 (Revision of IEEE Std C37.118-2005),
pp. 1–61, 2011.

[2] P. Kundur, N. J. Balu, and M. G. Lauby, *Power system stability and
control*. Vol. 7. New York: McGraw-Hill, 1994.