Component Selection

Choose model, subsystem, or subchart for analysis

If you have an existing model, subsystem, or subchart in Simulink^®, configure portions of your design for Simulink Design Verifier™ analysis. Use the bottom-up approach, analyzing smaller components first, for best results with a large or complex model. If you are just beginning your design process, see Design Considerations.

Functions

`sldvcompat`	Check model for compatibility with analysis
`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvisactive`	Verify updating of a block diagram

Model Checks

Simulink Design Verifier Checks

Topics

Basic Workflow for Simulink Design Verifier
Overview of the basic Simulink Design Verifier workflow.
Check Model Compatibility
Describes how to check whether your model is compatible with Simulink Design Verifier.
Handle Incompatibilities with Automatic Stubbing
How to use automatic stubbing.
Extract Subsystems for Analysis
Explains how subsystems and atomic subcharts are extracted for individual analysis.
Generate Test Cases for a Subsystem
Analyze an individual subsystem.
Analyze a Stateflow Atomic Subchart
Analyzing an atomic subchart using Simulink Design Verifier software.
Analyze a Model
Analyzing a simple example model with Simulink Design Verifier.
Analyze a Large Model
Describes techniques for analyzing a large model.
Configuring S-Function for Test Case Generation
This example shows how to compile an S-Function to be compatible with Simulink® Design Verifier™ for test case generation.
Bottom-Up Approach to Model Analysis
Explains the benefits of analyzing a model starting with low-level elements.
Design Verifier Pane
Specify analysis options and configure Simulink Design Verifier output.
Simulink Design Verifier Options
Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.
Simulink Design Verifier Block Library
Accessing the Simulink Design Verifier block library.
Support Limitations for Simulink Software Features
Lists Simulink software features that Simulink Design Verifier does not support.
Supported and Unsupported Simulink Blocks in Simulink Design Verifier
Lists Simulink blocks that Simulink Design Verifier does and does not support.
Support Limitations for Model Blocks
Simulink Design Verifier supports the Model block with some limitations.
Support Limitations for Stateflow Software Features
Lists the Stateflow^® software features that the Simulink Design Verifier and Fixed-Point Designer™ software does not support.
Support Limitations for MATLAB for Code Generation
Lists limitations associated with Simulink Design Verifier software support for MATLAB^® for code generation.
Support Limitations and Considerations for S-Functions and C/C++ Code
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.