Main Content

Design Range Checks

Check for specified minimum and maximum signal values


sldvextractExtract subsystem or subchart contents into new model for analysis
sldvoptionsCreate design verification options object
sldvrunAnalyze model
sldvreportGenerate Simulink Design Verifier report
sldvmakeharnessGenerate harness model


What Is Design Error Detection?

Explains the design error detection analysis option.

Derived Ranges in Design Error Detection

Explains the concepts of design ranges and derived ranges with regard to design error detection.

Run a Design Error Detection Analysis

Describes the recommended workflow for detecting design errors.

Check for Specified Minimum and Maximum Value Violations

Describes how to analyze the model to verify that specified design minimum and maximum values are honored.

Design Verifier Pane

Specify analysis options and configure Simulink® Design Verifier™ output.

Design Verifier Pane: Design Error Detection

Specify options that control how Simulink Design Verifier detects runtime errors in the models it analyzes.

Simulink Design Verifier Options

Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.

Review Analysis Results

Review analysis results in the Simulink Design Verifier  Results Summary window.