Configure Versal Design Using SoC Model Creator

To open the SoC Model Creator tool, enter the socModelCreator command at the MATLAB^® command prompt. In the window that opens, select the reference design for which you want to create an SoC model. Select the type of model and customize the model by using the predefined internal interfaces, external input/output (I/O) interfaces, and AXI registers.

Reference Design General

In the Reference Design General section, select the reference design board, reference design name, supported Vivado^® version, programming method, and target frequency.

• Reference design board — Select the target hardware board for your reference design as Xilinx Versal AI Core Series VCK190 Evaluation Kit.

• Reference design name — Select the reference design for which you want to create an SoC model. These are the reference design options for Xilinx^® Versal^® VCK190 evaluation kit:

  • Default System with SoC Blockset Generic Design (default) — Select this option when your design requires any or all of these interfaces: AXI4-Stream to software, software to AXI4-Stream, random access memory, interrupt, and/or AXI4 register.

  • Default system — Select this option when your design requires the AXI4 register interface only.

• Supported Vivado version — Select your Xilinx Vivado Design Suite from the list of supported Vivado versions.

  Set the synthesis tool path to point to an installed Vivado Design Suite by entering this command at the MATLAB command prompt. When you execute this command, use your own Xilinx Vivado installation path.

  hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath', ...
   'C:\Xilinx\Vivado\2022.1\bin\vivado.bat');

• Programming method — Set the method for programming the target hardware board to Ethernet or JTAG.

• Target frequency (MHz) — Specify the target frequency to modify the clock module setting in the reference design. The reference design uses a clock signal with the specified frequency. Specify a target frequency value in the range [5, 500]. The default value is 50.

Model Creation

In the Model Creation section, specify the name and type of your model.

• Top model name — Specify the name of the top model in SLX format. The default value is mySoCModel.slx.

• Create models representing — Select the type of the SoC model. The SoC model can be one of these types.

  • FPGA and processor (default) — Include an FPGA model, a processor model, and the register channel in your top model.

  • FPGA and memory — Include an FPGA model and a memory system in your top model. The memory system can contain a memory controller and memory channels or a specialized memory block, such as AXI4 Random Access Memory, AXI4-Stream to Software, or Software to AXI4-Stream.

  • FPGA only — Include an FPGA model in your top model.

Internal Interfaces

In the Internal Interfaces section, you can customize the model with interfaces defined in the selected reference design. Internal interfaces vary depending on the reference design that you select in the Reference Design General section.

For the Default System with SoC Blockset Generic Design reference design, you can customize the model with any or all of these interfaces in the single reference design.

• AXI Stream to Software

• Software to AXI Stream

• Random Access Memory

• Interrupt

External I/O Interfaces

In the External I/O Interfaces section, select the external I/O interfaces for your model from the list of available interfaces. These external I/O interfaces are board-specific and defined in the board definition file.

AXI Registers

In the AXI Registers section, you can add a new AXI register to your model by clicking New. Define the name, direction, data type, and dimension for the newly added register.

• Name — Specify the name of the register.

• Direction — Select the direction for the register as Write or Read.

• Data type — Select the data type for the register as int8, uint8, int16, uint16, int32, uint32, boolean, fixdt(1,16,0), fixdt(1,16,2^0,0), or a custom data type.

• Dimension — Specify the dimension of the register as a numeric scalar.

You can rearrange the register rows by clicking Move Up and Move Down. Select the row that you want to move up or down, then click Move Up or Move Down. To delete register, select the register and click Delete.

Click Create. A created SoC model opens in a Simulink^® window. The SoC model maps the input and output ports to the interfaces associated with the target board. You can add your algorithm to a subsystem in the created model for simulation, HDL code generation, and SoC deployment.

Note

After you create an SoC model for a specified reference design board, do not change the target hardware board. Even if you change the target board after you create an SoC model, the SoC Builder tool still generates HDL code for the target board for which you have created the model. To change the target hardware board, create a new SoC model for a required reference design board by using the SoC Model Creator tool.

You need not create a model again just to add an AXI register after you create the model. You can add the new AXI registers to the created model in Simulink and connect them to the Register Channel block in the top model.

Edit the created model to include the required algorithm. Navigate to the blocks marked FPGA Algorithm in the FPGA model or Processor Algorithm in the processor model. Replace these blocks with your own algorithm model. Then, simulate the system and use the SoC Builder tool to build software executables and an FPGA programming file from your model and program the target hardware board.