Generate Versal Design Using SoC Builder
This tutorial shows how to build hardware and software executables for your SoC model and execute your application on the supported Xilinx® Versal® ACAP devices. After you create an SoC model targeted for a Versal device using the SoC Model Creator tool, use the SoC Builder tool to generate an HDL IP, build a bitstream, and program the hardware board.
After you create an SoC model for a specified reference design board, do not change the target hardware board. Even if you change the target board after you create an SoC model, the SoC Builder tool still generates HDL code for the target board for which you have created the model. To change the target hardware board, create a new SoC model for a required reference design board by using the SoC Model Creator tool.
Set Up FPGA Design Software Tools
Set up your system environment for accessing Xilinx tools from MATLAB® by using the
hdlsetuptoolpath function. This function
adds the specified installation folder to the MATLAB search path. This example assumes that Xilinx
Vivado® is installed in the folder
hdlsetuptoolpath('ToolName','Xilinx Vivado', ... 'ToolPath','C:\Xilinx\Vivado\2022.1\bin\vivado.bat')
Prepare Model for Generation
Start the SoC Builder tool. In the Simulink® toolstrip, on the System on Chip tab, click Configure, Build & Deploy.
Prepare your model by selecting a starting point for the build process and then reviewing the model information.
If SoC Builder detects no support package, SoC Builder prompts you to install the required support package before going to the Setup section.
Select the starting point for the build process. If you are building a model for the first time, select Build using fixed reference design. If you have already completed the build process and saved the binaries in a folder, select Load existing binaries.
SoC Builder parses the model and displays the top model, the FPGA model, and the processor model (if one exists). Review this information for accuracy. If any of the information is incorrect, revise the model, save the model, and then restart the SoC Builder tool.
Select Build Action
In the Select Build Action section, select one of these build actions for your model and automate the build process.
Build, load, and run — Select this option to generate HDL and C code and to build software executables and an FPGA programming file from your model. After building, SoC Builder loads the generated code to the target hardware board and executes the application.
Build only — Select this option to generate HDL and C code and to build software executables and an FPGA programming file from your model. SoC Builder saves the generated binaries in a folder, and you can continue execution later.
Build and load for external mode — Select this option to build the design and run it in external mode. Use external mode to tune parameters on the FPGA without having to rebuild the FPGA design. You can also log data from the FPGA and display it on the host computer. For more information about external mode, see External Mode Simulations for Parameter Tuning, Signal Monitoring, and Code Execution Profiling (Simulink Coder).
Automate build process — Select this option to build your model with fewer clicks. Automating the build process performs these actions.
Skips these steps: select project folder, review hardware mapping, and review memory map
Runs these steps: validate, build, and load
All these steps use the inputs that you provided in the most recent build. If you are running the build process for the first time, SoC Builder uses default inputs for these steps.
Advanced build options — Select the build type as one of these options.
Processor and FPGA (default) — Build the processor and FPGA models in your top model.
Processor only — Build only the processor model in your top model.
FPGA only — Build only the FPGA model in your top model.
After you specify the build options, click Next.
Select Project Folder
Specify a path to a project folder by entering the path in the Project Folder box or by browsing to a folder location. SoC Builder places all of the generated files, including reports, executables, and the bitstream, in this specified folder.
If you select Load existing binaries as the starting point for the build process, specify the project folder location of the previous binaries and reports.
Review Hardware Mapping
Open the Hardware Mapping tool by clicking View/Edit.
View and edit the map of tasks in the SoC model to interrupt service routines (ISRs) on the hardware board.
This hardware mapping step of SoC Builder is visible only if you have an event-driven task defined in the Task Manager block in your top model.
Review Memory Map
Open the Memory Mapper tool by clicking View/Edit.
Review the base addresses and offsets. Edit the offsets if you need to. In this workflow, the Memory Mapper tool shows the device under test (DUT) and its registers.
This memory map step of SoC Builder is visible only if you have an FPGA model in your top model. If your FPGA model is set to frame-based modeling, then no FPGA model is visible. In this case, you cannot access the Memory Mapper tool.
Check the model against the selected board by clicking Validate.
To generate a bitstream for your FPGA design and a compiled executable for your software, click Build.
Clicking Build opens an external shell and runs third-party tools for synthesis and implementation of the design. The generation time depends on the complexity of your model and your host computer.
Review the IPv4 address, SSH port number, and login credentials. Edit any of these values if needed. This step is critical if you have more than one board connected to the host computer. SoC Builder requires this information to identify the correct port connection. Verify that the displayed IP address matches the IP address of the board you intend to use.
Verify that the board is connected to the host with an Ethernet cable, and then click Test Connection to test the physical connection to the board.
Load and Run Application
If your top model includes an FPGA model, but no processor model, the Load and Run button is labeled Load instead.
Verify that your board is connected to the host computer via an Ethernet cable. Click Load and Run. This action loads the generated bitstream to the FPGA, programs the processor, and runs the application.
If you select Build and load for external mode in the Select Build Action step, this action loads the bitstream to the FPGA and opens the model in external mode. You can now choose signals for logging and monitoring or change tunable parameters. To run the application on hardware, in the Run on Hardware section, on the System on Chip tab, click Monitor and Tune. If you already built your design and loaded it onto an FPGA, click Connect. This action connects your Simulink model to the FPGA model.
SoC Builder | Hardware Mapping | Memory Mapper