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FPGA Data Reader

Capture data from live FPGA into Simulink model

  • Library:
  • Generated

  • FPGA Data Reader block


The FPGA Data Reader block communicates with a generated IP core on an FPGA to return captured data into Simulink®.

Before you run this block, you must generate the customized data capture components. Integrate the generated HDL IP core into your project and deploy it to the FPGA. The block communicates with the FPGA over a JTAG cable. Make sure that the JTAG cable is connected between the board and the host computer.

For a workflow overview, see Data Capture Workflow.

By default, the FPGA Data Capture Component Generator tool generates a data capture model that contains this block and a scope. If you have a DSP System Toolbox™ license, the captured data is streamed to the Logic Analyzer tool. Otherwise, the Scope block shows the captured data. You can add other blocks to the model for analysis, verification, and display.


The output ports of the FPGA Data Reader block correspond to the signals you requested to capture in FPGA Data Capture Component Generator. Set the data types for these ports in the Signal and Trigger Editor, opened from the block parameters.


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This output port indicates the current capture window. The value of this output port is an integer from 1 to the value of the Sample depth parameter.

This output port indicates the position of the trigger detection clock cycle within a capture buffer.


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The block returns one frame of data per time step, where the frame is the entire capture buffer for each signal. Each frame contains Sample depth values, as specified at generation time. The default sample time provides for unbuffering each frame into single samples, which results in a sample time of 1.


This parameter is read-only. It reflects the value you specified at generation time.

Specify the number of recurrences to capture. This value must be a power of two, up to Sample depth. A window depth is defined as Sample depth / Number of capture windows. Consider the Number of capture windows when setting the Sample depth, to allow for sufficient buffering.

Specify the number of trigger stages. This value must be an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. When you specify the Max trigger stages parameter, consider the maximum number of trigger stages in which you plan to configure the trigger conditions to capture data.

By default, the clock cycle when the trigger is detected is the first sample of the capture buffer. You can change the relative position of the trigger detection cycle within the capture buffer. A nondefault trigger position means that some samples are captured before the trigger occurs. You can set this parameter to any number between 0 and window depth–1, inclusive. When the trigger position is equal to the window depth–1, the last sample corresponds to the cycle when the trigger occurs. If Number of capture windows is greater than one, the same trigger position applies to all windows. See Triggers.

This parameter is indicated by the logic gate icon. Press the Change operator button to toggle between AND and OR.

The trigger condition can be composed of value comparisons of one or more signals. Combine these value comparisons with only one type of logical operator. Suppose three signals, A, B, and C, make up the trigger condition. The options are:

A == 10 AND B == 'Falling edge' AND C == 0

A == 10 OR B == 'Falling edge' OR C == 0
You cannot mix and match the combination operators. See Triggers.

This parameter is read only. The signal names you specified at generation time are listed in the drop-down menu at the bottom. Click the + button to add a signal to the trigger condition.

To compare signals, select one of these operators: ==, !=, <, >, <=, or >=. To compare signals containing X or x (don't-care value), specify either == or != operator.

The trigger condition can be composed of value comparisons of one or more signals. This parameter specifies the value to match for each signal.

For a multi-bit signal, specify a decimal, binary, or a hexadecimal value within the range of the data type associated with the signal. While providing hexadecimal or binary values, you can provide values with a combination of X or x (don't care value) to enable bit masking. That means, while comparing the values, the trigger condition discards the place values with X or x and provides the output.

To separate a group of bits for better readability, you can use _ between bits. For example, you can represent a 32-bit binary value as 0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX and a 32-bit hexadecimal value as 0xAB_CDEXFX.

For boolean signals, select a level or edge condition. See Triggers.

Within this many FPGA data capture (FDC) IP core clock cycles, the trigger condition must occur in a trigger stage in which you are enabling this parameter. You can specify any integer value from 1 to 65,536 according to your requirements. Select this parameter to enable trigger time out in a trigger stage. A trigger time out is not allowed in Trigger Stage 1.

If a trigger condition is enabled, but the HDL IP core does not detect the condition, the data capture request times out after this many seconds. No data is returned to Simulink.

Data Types

This parameter is read only. It reflects the name of the Capture_Window output port, the name of the Trigger_Position output port, and the signal names you specify at generation time.

This parameter is read only. It reflects the value you specified at generation time.

The Data Type menu provides data type suggestions that match the bit width of the captured signal. This size is the width you specified for the port on the generated IP. You can type in this field to specify a custom data type. If the signal is 8, 16, or 32 bits, the default is uint. If the signal has one bit, the default is boolean. If the signal is a different width, the default is numerictype(0,bitWidth,0).

If your development board has multiple FPGAs or multiple JTAG connections, the data capture software cannot detect the location of your FPGA in the JTAG chain. Specify these advanced parameters to locate the FPGA that contains the data capture IP core.

Advanced Board Setup

Name of the JTAG cable used for data capture, specified as a character vector. Use this parameter when the board is connected to two JTAG cables of the same type.

Introduced in R2017a