ADC Common

Use the ADC Common options to set the common ADC parameters.

ADC Prescaler

The option to select the frequency of the clock, PCLK2, to ADC. PCLK2 is derived from system core clock and can have a maximum frequency of the clock as 84 MHz. When you select the clock core to ADC, the default value of frequency for ADC is set to 48 MHz (PCLK2 divided by 2)

Settings

Default: PCLK2 divided by 2

Delay between two sampling phases

The option to select the minimum delay that separates two ADC conversions in interleaved mode.

Settings

Default: 5 * T_ADCCLK

Enable temperature sensor and V_Refint channel

The option to enable the temperature sensor and the V_Refint channel.

Settings

Default: off

Enable V_BAT channel

The option to enable the V_BAT channel.

Settings

Default: off

ADC modules synchronization

The option that you select for ADC module synchronization. The different options you available are:

  • Single mode: All ADCs are independent — Select this option when the three ADCs must perform the conversion independently.

  • Dual mode: ADC1 and ADC2 combined, ADC3 independent — Select this option when you want to combine ADC1 and ADC2 and ADC3 to perform conversion independently.

  • Triple mode: ADC1, ADC2, and ADC3 combined — Select this option when you want to combine ADC1, ADC2, and ADC3 together for conversion.

Settings

Default: Single mode: All ADCs are independent

Multi ADC mode selection

The option that you select for multi-ADC mode.

Settings

Default: Regular simultaneous and injected simultaneous

See Also

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