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Access FPGA External Memory Using MATLAB as AXI Master over PCI Express

This example shows how to use MATLAB™ as AXI Master over PCI Express (PCIe) to access the external memory connected to an FPGA. The FPGA includes a Xilinx DDR memory controller for accessing the DDR memory. This memory controller provides an AXI4 slave interface for read and write operations by other components in the FPGA. The PCIe based MATLAB as AXI Master feature provides an AXI Master object that can be used to access any memory mapped location in the FPGA. This example shows how to integrate PCIe based MATLAB as AXI Master into a Xilinx Vivado project, and read or write to the DDR memory using MATLAB.


  • Xilinx® Vivado® of compatible version

  • Xilinx Kintex UltraScale+ FPGA KCU116 Evaluation Kit

  • HDL Verifier™ Support Package for Xilinx FPGA Boards

  • Host machine(PC) with PCIe slot

  • USB-JTAG cable

Set Up

Step 1: Set up FPGA board. Make sure that the Xilinx KCU116 board is connected to the host computer via both PCI Express and JTAG cable. The JTAG cable is used for programming the device.

Step 2: Prepare example in MATLAB. Set up the Xilinx Vivado tool path. Use your own Xilinx Vivado installation path when executing the command. For example:

>> hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2018.2\bin\vivado.bat');

Create a folder outside of the scope of your MATLAB installation. This folder must be writable. This example assumes that the folder is at C:\MyTests.

Start MATLAB and set the current directory in MATLAB to the folder you created. For example:

>> cd C:\MyTests

Copy the example files into current directory by executing this command in MATLAB.

>> copyXilinxFPGAExampleFiles('pcieaximaster')

Next, create a Vivado project. The following MATLAB command creates a Vivado project named "pcieaximaster.xpr" and contains the IP Integrator block diagram and constraint files.

>> system('vivado -mode batch -source createproject.tcl')

Step 3: Add IP to IP repository. To use the MATLAB as AXI Master IP inside Vivado's IP Integrator, add the folder that contains the IP to the project's IP repository path setting. You can add the path to the project from within MATLAB with this command:

>> setupAXIMasterForVivado pcieaximaster.xpr

Open the project in GUI mode by double-clicking the project in a file browser, or by execute this command in MATLAB:

>> system('vivado pcieaximaster.xpr &')

Step 4: Add PCIe MATLAB as AXI Master IP to the FPGA design.

In the Vivado GUI, open the block diagram design file You can find it in the source file sub-window.

Set the address of xdma_0 (AXI Bridge Subsystem for PCI Express) and ddr4_0 (memory controller) as shown:

Alternatively, you can complete the above setup steps by executing Tcl commands in Vivado.

source ./modifydesign.tcl

Step 5: Generate FPGA programming file and program the FPGA. To generate the FPGA programming file, click "Generate Bitstream" in the Vivado.

Program the FPGA through MATLAB using the following command:

>> filProgramFPGA('Xilinx Vivado','pcieaximaster.runs\impl_1\design_1.bit',1)

Step 6: After programming the FPGA, reboot the host machine.

Read and Write Operations to the FPGA

Once the design is running on the FPGA board, you can read and write into the AXI slaves connected to the PCIe based MATLAB as AXI Master IP. In this example, the data is written to the DDR memory connected to the FPGA, and retrieved back into MATLAB.

First, create the AXI master object in MATLAB

>> h = aximaster('Xilinx', 'interface', 'pcie');

Then, you can write and read from memory locations on the FPGA. The following two lines use the AXI Master object "h" to write "100" to address 0, and then read from address 0 of the memory.

>> writememory(h, 0,100)
>> readmemory(h, 0,1)