When using PCI Express® MATLAB as AXI Master, you must first include the following two intellectual property blocks (IPs) in your Xilinx® Vivado® project.
PCIe MATLAB as AXI Master IP
PCI Express Core
PCIe MATLAB as AXI Master is an HDL IP provided by MathWorks®. This IP connects the PCI Express (PCIe) core to your application code. The IP has a configuration port for accessing configuration registers. This block diagram shows the interface to the HDL IP. To know how to include the PCIe MATLAB as AXI Master IP in your FPGA design, see Set Up MATLAB as AXI Master.
The interface includes the following parts:
resetn are the clock and
reset inputs. Connect them to the AXI clock and reset.
axs_s0 is a 32-bit slave interface and is used for
accessing the PCIe configuration registers. Connect this interface to the
UltraScale+™ FPGA KCU116 memory mapped
axm_pcie is a 128-bit AXI master interface. Connect
this interface to the S_AXI_B slave port on the PCIe core.
axm_app is a 128-bit AXI master interface. Connect this
interface to your application logic.
After instantiating this IP in your design, open the block parameters for configuration.
Configure these parameters:
AXI Address Width – This parameter is the address bus width. The IP supports 32-bit address.
AXI Data Width – This parameter is the data bus
width. The IP supports 128-bit or 256-bit data. Note that this parameter is
not identical to the data width of the
aximaster object or
the AXI Master
Read or AXI Master
Write blocks. If the data width is set to 32 bits, and the
AXI Data Width of your IP is set to 128 bits,
HDL Verifier™ packs four 32-bit words to transfer on the 128-bit bus.
ID Width – This parameter is the ID width in bits. Its value must match the ID width of the AXI slave.
The DMA/Bridge Subsystem for PCI Express Core is a board-specific IP provided by Xilinx. Use this IP for configuring and integrating the PCI Express port. For more information on how to include this IP in your FPGA design, see Set Up MATLAB as AXI Master.
After instantiating the PCIe core HDL IP in your Xilinx Vivado project, configure the PCIe core using these steps. This example is for a Kintex UltraScale+ FPGA KCU116 board.
On the Basic tab, set the parameters as shown in this figure.
On the PCIe ID tab, set the parameters as shown in this figure.
The ID Initial Values listed in the PCIe tab screen are the required PCIe ID settings to ensure compatibility with MathWorks PCIe device driver for Xilinx FPGA boards.
Connect the PCIe MATLAB as AXI Master IP to the PCIe core. This example shows theKintex UltraScale+ FPGA KCU116 DMA/Bridge Subsystem IP for PCI Express.
Compile and build your FPGA project.
Insert the FPGA board into the PCI Express slot on the motherboard of the host machine.
Program FPGA with the bitstream generated for your design.
Restart the host machine.
Once the program is running on your FPGA board, you can create a MATLAB® AXI master object in your MATLAB command window. For more information, see
aximaster. To access the slave memory locations on the board, use the
writememory functions of