ADAU1761 Codec
Connect hardware logic to ADAU1761 signals on hardware board
Add-On Required: This feature requires the SoC Blockset Support Package for Xilinx Devices add-on.
Libraries:
SoC Blockset Support Package for Xilinx Devices /
Zynq-7000 /
ZedBoard
Description
The ADAU1761 Codec block connects your hardware logic to the ADAU1781 codec on the hardware board. When you include this block in your design, the SoC Builder tool generates a constraint file to map the pins of the FPGA to the codec pins. Of the supported boards, only ZedBoard™ includes the ADAU1761 codec. This board uses the I2C interface to connect the FPGA and the audio codec, so your design must connect the ADAU1761 Codec block to an I2C Master block.
Limitations
In the hardware setup, set Hardware Board to
ZedBoard
and set Add-on Card toNone
.This block supports SoC generation using the SoC Builder tool. This block does not support the IP core generation workflow. For more information on workflows, see SoC Generation Workflows.
Ports
Input
Output
Extended Capabilities
Version History
Introduced in R2019a