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Target Deep Learning Processor and Image Preprocessing to FPGA

The support package includes two reference designs for deep learning (DL) applications. When you use a deep learning reference design, you must specify the name and file location of a deep learning processor core generated by using the Deep Learning HDL Toolbox™ tools.

This page describes the Deep Learning with Preprocessing Interface reference design. This reference design connects a DL processor with custom preprocessing logic. These two parts of the design communicate control information over an AXI manager interface, and share video data using a second AXI manager interface to DDR memory. The reference design expects input data over an AXI Stream interface and writes the processed data back to DDR memory. The Deploy and Verify YOLO v2 Vehicle Detector on FPGA example shows how to use this reference design, and how to model the AXI interfaces and the handshaking logic between the preprocessing logic and the DL processor. In the example, the deployed design is controlled by a MATLAB host machine that provides input video data, reads the output data, and verifies the results.

For a reference design that processes live HDMI video and adds postprocessing operations in the ARM processor, see Deep Learning Processing of Live Video.

This diagram shows the interfaces in the Deep Learning with Preprocessing Interface reference design.

The FPGA user logic for this reference design must contain two simplified AXI Manager protocol interfaces. One interface interacts with the DL IP core and the other transfers data between the FPGA user logic and DDR.

  • AXI-Lite — The MATLAB host uses AXI-Lite registers to monitor and control the FPGA.

  • AXI4-Stream — Map the input pixel data and pixelcontrol bus to the data port of an AXI4-Stream subordinate interface. The pixel data and control signals are packed into a uint32 data word. In the Deploy and Verify YOLO v2 Vehicle Detector on FPGA example, the MATLAB host provides input data to this interface.

  • AXI4 Manager of DDR — The FPGA user logic writes output data to the PL DDR memory using this interface. The deep learning IP then reads the data for processing.

  • AXI4 Manager of deep learning IP — The FPGA user logic and the deep learning IP communicate control information over this interface. The FPGA user logic must contain logic for the handshaking protocol of the deep learning IP. The Deploy and Verify YOLO v2 Vehicle Detector on FPGA example includes a subsystem that shows how to model this handshake protocol.

This reference design does not support video capture to Simulink®.

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