Video Capture HDMI
Import live video frames from HDMI FMC card on Zynq-based
Since R2023a. Replaces Video Capture and Video Capture (software interface).
Libraries:
Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware
Description
The Video Capture HDMI block imports video frames from a Zynq®-based board that has an HDMI FMC card into your Simulink® model. The support package programs the FPGA with an image that includes data path multiplexers, video format conversions, and a video test pattern generator (TPG). You can control these data path and conversion options from the Video Capture HDMI block.
To capture video from a Zynq-based board that has a MIPI® FMC card, use the Video Capture MIPI block.
Points A
and B
in the diagram show the options for capturing video into
Simulink or an ARM® processor. The FPGA user logic section is the IP core that you
generate from your design using HDL Workflow Advisor. You can capture the input video before the
FPGA user logic, or the output video after the FPGA user logic. If you enable the bypass of the
FPGA user logic, or if you have not generated any FPGA user logic, the two capture locations show
the same data.
The video data is a pixel stream on the FPGA, but when you capture the video to Simulink, the stream is converted to frame-based video.
The reference design requires the same video resolution and color format for the entire data path. The resolution you select for the Video Capture HDMI block must match that of your camera input. The design you target to the FPGA user logic must not modify the frame size or format of the data.
When you use this block in a model deployed with the default FPGA image, you can change the video format that is imported to the ARM processor.
The HDL Workflow Advisor generates a software interface model that contains the Video Capture HDMI block. The parameter settings of the generated block match the settings of the Video Capture HDMI block in your original model. You can change the input video resolution, switch between HDMI input or an on-chip test pattern generator, and enable an optional bypass of the user logic section of the FPGA. When you change a parameter, the block writes an AXI-Lite register on the board.
You can also deploy this block to an ARM processor to capture the video from the FPGA user logic into the ARM for further processing. When you use the block this way, the settings on the block must match those of the deployed FPGA image.
To use this block in the generated software interface model, or to create your own model to target an ARM processor, you must have the Embedded Coder® product and the Embedded Coder Support Package for Xilinx® Zynq Platform.
Capture from Deep Learning Reference Designs
When you use the RGB with DL Processor
reference design, you can
deploy the design and then open a simple capture model, such as the Getting Started with Vision Zynq Hardware model, to capture
video while the design runs on the board. The video captured is the result of the postprocessing
operation in the ARM processor. To capture video from this reference design, set the Video
Capture HDMI block parameters to these values.
Video source must be
HDMI input
. This reference design does not contain a test pattern generator.Frame size must be
1080p HDTV (1920x1080p)
.Pixel format must be
RGB
.The Bypass FPGA user logic and Capture point parameters have no effect with this reference design.
For an example, see YOLO v2 Vehicle Detector with Live Camera Input on Zynq-Based Hardware.
Ports
Output
Parameters
Version History
Introduced in R2023a