How to divide tasks to be done by Nios II processor & Logic elements?

Hi all,

I have a complete working project where I use MATLAB/Simulink with coding in S-function Level 2 as well as Simulink blocks.

Now I would like to convert the above project into C AND VHDL to be implemented on a hardware FPGA design on DE0 Nano Development board, Cyclone IV E. I am using Quartus II, SOPC builder, Nios II IDE or Altera monitor program.

In my Matlab project, basically what I was doing is to have thousand of inputs, sort them ascending/descending, do some comparison if-else, arithmetic operations, produce outputs, switching on/off devices. (I could give more details about this, the number of inputs/outputs could be reduced to the size permissible by hardware)

What I know: I am going to use BOTH the Nios II processor AND the logic elements on the development board, meaning I need to program Nios II using C language AND also program those logic elements using VHDL.

What I don't know: My question is, how do I determine which tasks are to be done by Nios II processor and which tasks are to be done by logic elements? Is there specific rule to follow or is it totally up to the programmer to decide? But I guess there should at least be some basic rules to adhere?

Forgive me if this really sounds stupid as I am really new to FPGA design as well as VHDL.

Hopefully someone could give me some inputs at least to get started. Thank you in advance.