HDL Coder - Generate RTL Code and IP Core ERROR

Hi,

I am trying to run HDL work flow adviser for the standard LED blink example from MATLAB. I am new to this style of programming FPGA, can someone advice me what to do or where I can find a solution. This is the following error:

Failed

Run "Vivado IP Packager" Attempt Unsuccessful. Synthesis Tool Log:

**** Vivado v2015.2 (64-bit) ** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 ** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source vivado_ip_package.tcl # create_project prj_ip {} -part xc7z020clg484-1 -ip -force INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/FPGA_Programming/hdl_prj/ipcore/hdlcoder_led_blinking_led_counter_ipcore_v1_0/prj_ip' # set_property ip_repo_paths {../../} [current_fileset] # ipx::infer_core -name {prj_packager} -directory {../prj_packager} {../} ERROR: [Common 17-158] 'directory' can only be specified once. INFO: [Common 17-206] Exiting Vivado at Fri Sep 25 13:51:21 2015...

Elapsed time is 8.5704 seconds.

Regards, Anirudh

Answer 1

[Tim McBrayer]

This error is coming directly from Xilinx Vivado, and seems pretty clear. For whatever reason, Xilinx wants your project root directory to have fewer than 80 characters in its name. The name you are using is 'C:/FPGA_Programming/hdl_prj/ipcore/hdlcoder_led_blinking_led_counter_ipcore_v1_0/prj_ip', which is 87 characters long:

 >> length('C:/FPGA_Programming/hdl_prj/ipcore/hdlcoder_led_blinking_led_counter_ipcore_v1_0/prj_ip')
 ans =
    87

The solution is obvious; shorten this path however you can, or use the subst command as suggested.