Answered
Display the RST port in a Xilinx FIL model
You'll have to create another "reset" signal as "data" port to use it in Simulink. FIL requires a dedicated reset signal so that...

8 years ago | 0

| accepted

Answered
HDL Parser error: Unsupported data-type sfixed in "Fpga-in-the-loop"
To use FPGA-in-the-Loop, the I/O port on the top-level entity must be std_logic_vector or std_logic type. The ufixed and sfixed ...

8 years ago | 0

Answered
Co-simulation with HDL verifier and Modelsim version
The list of supported ModelSim versions are not exclusive. Other versions of ModelSim SE/PE/DE are likely to be compatible, but ...

8 years ago | 0

| accepted

Answered
HDL Verifier and FPGA in the loop
There is a trouble shooting section in the HDL Verifier documentation. Try to see if that one helps you. It's possible a network...

9 years ago | 0

Answered
cosimWizard problems in order to do a cosimulation Simulink/ModelSim
The error occurs since ModelSim cannot find Altera LPM library. To use the Altera LPM library, you need to compile that libra...

9 years ago | 0

| accepted