PROC_HILs is a hardware-in-the-loop acceleration tool for running Simulink designs on FPGAs. It can automatically translate Simulink designs into FPGA code and run them as part of a Simulink simulation. The generated code is compatible with the PROC board installed on the target PC, and has the synchronization code needed to communicate with Simulink. The conversion of the Simulink models into HDL code is accomplished by either Simulink® HDL Coder or Altera DSP Builder, along with GiDEL tools. The simulation of a Simulink design, or any part of it run on a high-capacity, high-speed PROC board is significantly accelerated.
To enable PROC_HILs the user adds a generation block to the design. PROC_HILs works in two phases: the preparation phase and the simulation phase.
In the preparation phase, clicking on the GiDEL generation block opens the PROC_HILs interface. Pressing the Go button will automatically:
In the simulation phase, the user may run the generated model accelerated by the FPGA or the original model.
Advanced users can stop the automatic process and have manual control over the different stages providing a variety of options, such as adding legacy HDL designs and operating target system designs run from users' C++ programs.