SerDes Toolbox

Design SerDes systems and generate IBIS-AMI models for high-speed digital interconnects

 

SerDes Toolbox™ provides a MATLAB® and Simulink® model library and a set of analysis tools and apps for the design and verification of serializer/deserializer (SerDes) systems or high-speed memory PHYs such as DDR5.

With the SerDes Designer app, you can use statistical analysis to rapidly design wired communications links. The app provides parameterized models and algorithms that let you explore a wide range of equalizer configurations to improve channel performance. You can assess metrics such as eye diagram, bathtub curve, and channel operating margin (COM), including the effects of jitter and crosstalk. 

With MATLAB based building blocks such as CTLE, DFE, FFE, and CDR, you can describe your chosen architecture using datasheets or measurement data and simulate control and adaptative algorithms. White-box examples of typical applications such as PCIe, USB, Ethernet, and DDR provide reference designs that you can use as a basis for your own designs. 

SerDes Toolbox supports automatic generation of dual IBIS-AMI models for statistical analysis and time-domain simulation. These models can be used with third-party channel simulators for system integration and verification. 

Get Started:

SerDes Design

Design SerDes systems using parametrized white-box models and algorithms.

SerDes Designer App

Design, configure, and analyze SerDes systems using the SerDes Designer app. Model channel attenuation, dispersion, jitter, and crosstalk. Check performance metrics such as channel operating margin (COM), using reports, eye diagrams, bathtub curves, and other visualizations. Use MATLAB to automate analysis, reporting, and design space exploration. Generate Simulink and IBIS-AMI models for further refinement and verification.

PAM 4 SerDes system including adaptive CTLE and DFE.

Adaptive Equalizer Design

Use DFE, CTLE, FFE, AGC, and CDR to design adaptive equalizers. Use parametrized blocks and algorithms for single-ended and differential signals.

Starting with the white-box implementation, customize models with your own algorithms.

Explore local and global adaptation strategies to optimize your system performance, and generate IBIS-AMI models.

SerDes Analysis and Simulation

Perform statistical analysis with the SerDes Designer app and create a Simulink model for time-domain simulation.

Statistical Analysis

Perform statistical analysis to compute and visualize eye contours, bit error rates (BER), bathtub curves, COM, and other metrics using the SerDes Designer app.

Explore the design space of your equalization algorithms and channels using PAM4, PAM3, and NRZ modulations.

Simulink report of PAM4 SerDes system statistical analysis.

Time-Domain Simulation

Perform time-domain simulation of adaptive algorithms using customizable Simulink blocks and channel models that capture frequency-dependent attenuation, reflections, and arbitrary impulse responses.

Verify your equalization algorithms using pseudorandom binary sequences (PRBS) and custom stimulus patterns.

Simulink model generated with the SerDes Designer app for time-domain simulation.

IBIS-AMI Model Generation

Generate standard-compliant IBIS-AMI models for use in third-party channel simulators.

Dual Model Generation

Generate IBIS-AMI statistical (Init) and time-domain (GetWave) algorithmic models with associated analog IBIS models. Customize the model interface by managing IBIS-AMI parameters from the SerDes Designer app and Simulink.

Integration with Third-Party Channel Simulators

Import generated IBIS-AMI models into third-party channel simulators such as SiSoft Quantum Channel Designer™ (QCD) and Quantum-SI™ (QSI), Keysight™ ADS, Synopsys® HSPICE, Mentor Graphics® HyperLynx®, and Cadence® Sigrity SystemSI. Use IBIS-AMI models in your verification flow and share them with customers.

QCD results of an IBIS-AMI model generated with the SerDes Designer app.

Reference Designs

Use white-box blocks to model industry-standard communication protocols such as PCI Express, DDR, and Ethernet.

Standard-Compliant Reference Models

Use standard-compliant reference designs of PCIe Gen4, DDR5, and OIF CEI-56G. Get started with reference models and refine them to design next-generation communication protocols using NRZ and higher-order modulation schemes such as PAM3 and PAM4. Generate standard-compliant IBIS-AMI models for verification.

Latest Features

IBIS-AMI Jitter Analysis

Add IBIS-AMI jitter from SerDes Designer app

PAM3 Analysis

Use PAM3 modulation in SerDes Designer app

Eye Processing for Time Domain

Display time domain eye, clock times, and time domain metrics

AMI Parameters

Improved workflow for adding, hiding, and automatically managing AMI parameters

IBIS-AMI Clock Times Block

Generate clock times for custom DFECDR and CDR blocks

See release notes for details on any of these features and corresponding functions.