Microsemi FPGAs and SoCs 

Model, verify, and program your algorithms on Microsemi devices.

Domain experts and hardware engineers use MATLAB® and Simulink® to develop prototype and production applications for deployment on Microsemi® FPGA and SoC devices. With MATLAB and Simulink, you can: 

  • Model hardware architecture at the system level
  • Program your FPGA without writing any code
  • Simulate and debug your FPGA using MATLAB and Simulink tools
  • Perform production FPGA and SoC design

“As a mechatronic systems engineer, my expertise is in control systems and their models, not HDL and FPGAs. With Model-Based Design, I can use my insight and knowledge of the controller and the system being controlled to do more of the work normally done by FPGA engineers and reduce their workload.”

Rob Reilink, DEMCON

Using MATLAB with Microsemi FPGAs and SoCs 

Modeling for FPGA Programming 

Add hardware architecture to your algorithm using MATLAB and Simulink. This includes fixed-point quantization (30:34), so you can use resources more efficiently, and native floating-point (8:55) code generation, so you can more easily program FPGAs. Reuse your tests and golden reference algorithm to simulate each successive refinement.

HDL Coder™ generates synthesizable VHDL or Verilog directly from HDL-ready Simulink and MATLAB function blocks for applications such as signal processingwireless communicationsmotor and power control, and image/video processing

Programming Microsemi FPGAs and SoCs

HDL Coder guides you through the steps to program your FPGA or SoC directly from Simulink without having to write a single line of code. From HDL Coder, you can optimize and generate synthesizable VHDL or Verilog along with AXI interfaces to plug into an SoC. From there you can call Embedded Coder to generate C/C++ to program the software that runs on the embedded processor.

Using HDL Coder, you can specify your Microsemi FPGA as the target device. You can automatically create a Libero® SoC Design Suite project, perform synthesis, and run place and route. 

FPGA Simulation and Debugging

HDL Verifier reuses your MATLAB and Simulink test environments to verify your FPGA design. 

With cosimulation (5:35), you can automatically run your MATLAB or Simulink test bench connected to your Verilog or VHDL design running in a simulator from Mentor Graphics or Cadence Design Systems.

FPGA-in-the-loop simulation connects your MATLAB or Simulink test bench to supported Microsemi FPGA boards via Ethernet. 

Test your implemented design in your MATLAB or Simulink test bench.

Production FPGA and SoC Design

Domain experts and hardware engineers use MATLAB and Simulink to collaborate on production FPGA and SoC design for wireless, image/video processing (20:59), motor and power control (24:20), and safety-critical applications.

HDL Coder high-level synthesis optimizations (49:42) help you meet your design’s goals while maintaining traceability between the generated RTL, the model, and the requirements, which is important for high-integrity workflows such as DO-254. Along with synthesizable VHDL and Verilog, HDL Coder generates IP cores that easily plug into Libero for system integration. And HDL Verifier generates verification models (5:19) that help speed test bench development.