MISRA C:2012 Rule 13.2
The value of an expression and its persistent side effects shall be the same under all permitted evaluation orders and shall be independent from thread interleaving
Description
Rule Definition
The value of an expression and its persistent side effects shall be the same under all permitted evaluation orders and shall be independent from thread interleaving.
Rationale
If an expression results in different values depending on the order of evaluation, its value becomes implementation-defined.
If an expression results in different values depending on order of thread-interleaving, then the value is unpredictable since the C standard does not specify any order for thread interleaving. Such unpredictable behavior implies your code might contain data race conditions, which is undefined behavior.
Polyspace Implementation
The rule checker reports a violation if an expression satisfies any of these conditions:
The same variable is modified more than once in the expression or it is both read and written.
The expression allows more than one order of evaluation.
The expression contains a single
volatile
object that occurs multiple times.The expression contains more than one
volatile
object.
Because volatile
objects can change their value at
anytime, an expression containing multiple volatile
variables or
multiple instances of the same volatile
variable might have
different results depending on the order of evaluation.
Troubleshooting
If you expect a rule violation but do not see it, refer to Diagnose Why Coding Standard Violations Do Not Appear as Expected.
Examples
Check Information
Group: Side Effects |
Category: Required |
AGC Category: Required |