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System Integration of Deep Learning Processor IP Core

Generate the deep learning (DL) processor IP core by using HDL Coder™ and Deep Learning HDL Toolbox™

You can integrate the deep learning processor IP core into your system by:

  • Generating and integrating DL Processor IP Core—Generate a generic deep learning processor IP core by using Deep Learning HDL Toolbox. The generated deep learning processor IP core is a generic HDL Coder IP core with standard AXI4 interfaces. You can integrate the generated generic DL IP core into your Vivado® or Quartus® design.

    Accelerate the integration of the generated DL processor IP core into your system design by:

    • Reading the AXI4 register maps in the generated IP core report. The AXI4 registers allow MATLAB® or other AXI4 Master devices to control and program the DL processor IP core.

    • Using the compiler generated external memory buffer allocation.

    • Formatting the input and output external memory data.

    Manually integrate generic DL processor IP core

  • Reference design based DL Processor IP core integration—Generate a generic deep learning processor IP core by using Deep Learning HDL Toolbox. Integrate the generated deep learning processor IP core into your custom reference design by using HDL Coder. See Deploy IP Core on Custom Hardware (HDL Coder). You can design the pre-processing and post-processing DUT logic in Simulink® or MATLAB, and use the HDL Coder IP core generation workflow to integrate the pre-processing and post-processing logic with the deep learning processor.

    Reference design based deep learning processor IP core integration

    Use MATLAB to run your custom deep learning network on the deep learning processor IP core and retrieve the deep learning network prediction results from you integrated system design.

Functions

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dlhdl.BitstreamBitstream information for deployment (Since R2024b)
loadInfoFromPluginLoad and update bitstream information using board and reference design plugin files (Since R2024b)
saveBitstreamInfoFileUpdate bitstream MAT file with information from bitstream object (Since R2024b)
dlhdl.WorkflowConfigure deployment workflow for deep learning neural network (Since R2020b)
compile Compile workflow object (Since R2020b)
deploy Deploy the specified neural network to the target FPGA board (Since R2020b)
getStatusRegisterList Retrieve names and descriptions of debug status registers (Since R2024a)
predictPredict responses by using deployed network (Since R2020b)
readStatusRegister Read debug status registers (Since R2024a)
dlhdl.ProcessorConfigure processor object to handle deep learning processor IP core input and output data (Since R2023b)
getExpectedPaddedInputData Pad input data for deep learning processor IP core (Since R2023b)
getUnpaddedOutputData Remove padding from deep learning processor IP core output data (Since R2023b)
dlhdl.ProcessorConfigure processor object to handle deep learning processor IP core input and output data (Since R2023b)
getInt8ToSingleConversionExponent Retrieve exponent value for int8-to-single data type conversion (Since R2024b)
getSingleToInt8ConversionExponent Retrieve exponent value for single-to-int8 data type conversion (Since R2024b)
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design
registerDeepLearningMemoryAddressSpace Add memory address space to reference design (Since R2021b)
registerDeepLearningTargetInterfaceAdd and register a target interface (Since R2021b)
validateReferenceDesignForDeepLearningChecks property values in reference design object (Since R2021b)
getStatusRegisterList Retrieve names and descriptions of debug status registers (Since R2024a)
readStatusRegister Read debug status registers (Since R2024a)

Blocks

Deep Learning HDL Processing SystemSimulate deep learning processor IP core interface (Since R2023b)
Deep Learning HDL Int8 To Single ConversionConvert 8-bit signed integer data to single-precision data (Since R2024b)
Deep Learning HDL Single To Int8 ConversionConvert single-precision data to 8-bit signed integer data (Since R2024b)

Topics

Generate and Integrate DL Processor IP Core

Reference Design-Based DL Processor IP Core Integration

Featured Examples