QSPI Controller Peripheral Configuration

R2026b

Map QSPI controller peripherals in the Infineon AURIX model to peripheral registers in the MCU

Since R2024a

Description

Add-On Required: This feature requires the Embedded Coder Support Package for Infineon AURIX TC3x Microcontrollers add-on.

View and edit the map of peripherals in the Infineon^® AURIX™ model to the hardware peripherals.

Using the Hardware Mapping tool, you can:

• View and edit configuration parameters for QSPI controller block.

• Configure the global parameters. To set the group peripheral, select peripheral in Browser > Peripherals > QSPI Controller . For more, see Map Tasks and Peripherals Using Hardware Mapping.

• Check for any conflicts between the peripherals.

Open the QSPI Controller Peripheral Configuration

In the Simulink^® toolstrip, go to Hardware tab and click Hardware Mapping.

Parameters

Global parameters > Module # > Events

Enable Tx FIFO event — Option to enable QSPI transmit buffer interrupt

off (default) | on

Select to enable the QSPI transmit FIFO interrupt.

Note

When you enable this parameter, the block handles data through interrupts. Therefore, you must use the QSPI Controller block with Transfer mode set to SPI Transmit or SPI Receive.

Tx FIFO mode — FIFO flag mode setting for transmit FIFO buffer

Read-only: Batch Move (default) | Single Move

This parameter is read-only.

Select one of these operation modes for transmit FIFO buffer:

• Single Move — Select this mode to generate an interrupt to refill the transmit buffer as soon as there is a free element.

• Batch Move — Select this mode to generate an interrupt if the FIFO level of transmit data exceeds above Tx FIFO threshold value.

Dependencies

To enable this parameter, select the Enable Tx FIFO event parameter.

Tx FIFO threshold — FIFO level for transmit FIFO event

1 (default) | 2 | 3 | 4

Specify FIFO level for the Tx FIFO event.

Dependencies

To enable this parameter, select the Enable Tx FIFO event parameter.

Enable Rx FIFO event — Option to enable receive buffer interrupt

off (default) | on

Select to enable the QSPI receive FIFO interrupt.

Note

When you enable this parameter, the block handles data through interrupts. Therefore, you must use the QSPI Controller block with Transfer mode set to SPI Transmit or SPI Receive.

Rx FIFO mode — FIFO flag mode setting for receive buffer

Read-only: Batch Move (default) | Single Move

This parameter is read-only.

Select one of these operation modes for the receive buffer:

• Single Move — Select this mode to generate an interrupt to fetch the received element as soon as possible.

• Batch Move — Select this mode to generate an interrupt if the filling level rises above Rx FIFO threshold value.

Dependencies

To enable this parameter, select the RxFifo event parameter.

Rx FIFO threshold — FIFO level for Rx FIFO event

0 (default) | 1 | 2 | 3

Specify FIFO level for Rx FIFO event.

Dependencies

To enable this parameter, select the Enable Rx FIFO event parameter.

Enable error event — Option to enable error interrupt

off (default) | on

Select to enables the QSPI error interrupt.

Note

When you enable this parameter, the block handles data through interrupts. Therefore, you must use the QSPI Controller block with Transfer mode set to SPI Transmit or SPI Receive.

Global parameters > Module # > Pin selection

Serial Clock pin (SCK) — Pin selection for serial clock

pin numbers

Select the pin number for the serial clock. The available pin numbers vary based on the module selected.

The QSPI Controller block outputs the clock signal, which all connected QSPI peripheral devices use as the primary timing source.

Serial Data Out pin (SDO) — Pin number to transmit serial data

pin numbers

Select the pin number for the serial data to be transmitted to QSPI peripheral devices. The available pin numbers vary based on the module selected.

Serial Data In pin (SDI) — Pin number to receive serial data

pin numbers

Select the pin number for the serial data to be received from QSPI peripheral devices. The available pin numbers vary based on the module selected.

Global parameters > Module # > Common pin properties

Input pins pull — Configuration mode of QSPI input pin

Pull-down (default) | Tri-state | Pull-up

Select the configuration mode of QSPI input pin.

Output pins strength — Configuration mode of QSPI output pin

Push pull (default) | Open-drain

Select the configuration mode of QSPI output pin.

Speed — Speed for QSPI pin

Speed-1 (default) | Speed-2 | Speed-3 | Speed-4

Select the pin speed for QSPI pins.

Voltage level — Voltage level for QSPI pin

Automotive (default) | TTL-5V | TTL-3.3V

Select voltage level of the QSPI pins.

Module

Module — Option to select the QSPI controller module

0 (default) | 1 | 2 | 3 | 4

Select the controller module for QSPI communication.

Tx mode

Tx mode — QSPI transmission mode

Continuous (default) | Single transfer

Select one of these transmission modes.

• Continuous — Transmits all data elements in a single uninterrupted frame. The QSPI controller block keeps the chip select signal active for the entire duration of the data transfer.

• Single-transfer — Transmits each data element as an individual transfer frame. The QSPI controller block deactivates the chip select signal after each data element is transferred.

Clock

Baud rate — Configure baud rate for QSPI communication

1000000 (default) | positive scalar integer

Specifies the rate of data communication between the QSPI Controller and QSPI the Peripheral blocks.

Data heading (Endianness) — Byte ordering format used by the QSPI Controller while transmitting or receiving multi‑byte data element

MSB first (default) | LSB first

Select the QSPI data heading in binary numbers.

• LSB first — SDO pin outputs the least significant bit (LSB) first, then transmits the remaining bits from right to left.

• MSB first — SDO pin transmits the most significant bit (MSB) first, then transmits the remaining bits from left to right.

Polarity — Clock polarity in idle state

Idle low (default) | Idle High

Specify idle level of the serial clock signal generated by the QSPI Controller.

Phase — Serial clock edge for QSPI communication

Trailing edge (default) | Leading edge

Specify clock edge for QSPI communication.

Enable parity — Option to enable QSPI clock parity

off (default) | on

Select to enables the QSPI clock parity.

Parity — Clock parity bit type

Even parity (default) | Odd parity

Specify the QSPI clock parity.

Dependencies

To enable Parity parameter, select the Enable parity parameter.

Enable simplex — Option to enable simplex communication

off (default) | on

Enable to configure the QSPI Controller block to transmit data continuously.

Dependencies

To enable this parameter, set the Transfer mode parameter to SPI Transmit in the QSPI Controller block in the Simulink model.

Chip Select (CS)

CS pin — Chip select (CS) output pin for the QSPI peripheral device

options vary based on the module selected

Select the chip select output pin for the QSPI peripheral devices.

CS active level — QSPI chip select logic levels

Low (default) | High

Select the chip select logic level to enable or disable the QSPI peripheral devices.

CS timing parameters in clock ticks

CS lead delay — Chip select lead delay for the QSPI peripheral device

0.0 (default) | 0.5 | 1 | 1.5 | 2 | 2.5 | 3 | 3.5

Specify the delay between the CS pin's active edge and the first shift clock edge.

CS trail delay — QSPI chip select trail delay for the QSPI peripheral device

0.0 (default) | 0.5 | 1 | 1.5 | 2 | 2.5 | 3 | 3.5

Specify the delay between the data block’s shift clock period and the deactivating edge of the CS pin. If you set Tx mode to Continuous, this parameter can also represent delay between the data block’s shift clock period and the start of a new data block.

CS inactive delay — Delay between CS deactivation and the next transfer

0.0 (default) | 0.5 | 1 | 1.5 | 2 | 2.5 | 3 | 3.5

Specifies the delay inserted after the end of the last trailing phase of a QSPI data frame.

Version History

Introduced in R2024a