Adaptive pipelining

Insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device

Model Configuration Pane: Optimization / Pipelining

Description

Use this parameter to insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.

Dependencies

When you specify this parameter, in the HDL Code Generation > Target pane, specify the Synthesis Tool. If your design has multipliers, specify the Synthesis Tool and the Target Frequency (MHz) for adaptive pipeline insertion.

Settings

Off (default) | On

On

Insert adaptive pipeline registers in your design. For HDL Coder™ to insert adaptive pipelines, you must specify the synthesis tool.

Off

Do not insert adaptive pipeline registers.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the AdaptivePipelining setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdl function.

  makehdl('sfir_fixed/symmetric_fir', ... 
                      'AdaptivePipelining','on')

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

  hdlset_param('sfir_fixed','AdaptivePipelining','on')
  makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: AdaptivePipelining

Type: character vector

Value: 'on' | 'off'

Default: 'off'

Version History

Introduced in R2016b