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Map lookup tables to RAM

Lookup tables in your design to block RAM and reduce area usage on the target FPGA device

Since R2021b

Model Configuration Pane: Optimization / Pipielining

Description

Use this parameter to map lookup tables in your design to block RAM and reduce area usage on the target FPGA device.

Dependencies

When you specify this parameter, in the HDL Code Generation > Target pane, specify the Synthesis Tool.

Settings

On (default) | Off
On

Map lookup tables in your design to RAM.

Off

Do not map lookup tables in your design to RAM.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the LUTMapToRAM setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        'LUTMapToRAM','on')

  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','LUTMapToRAM','on')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommendations.

Programmatic Use

Parameter: LUTMapToRAM
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2021b