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Single Port RAM

Single port RAM

  • Single Port RAM block

HDL Coder / HDL RAMs


The Single Port RAM block models RAM that supports sequential read and write operations.

If you want to model RAM that supports simultaneous read and write operations, use the Dual Port RAM block or Simple Dual Port RAM block.



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Data that you write into the RAM memory location when we is true. The data inherits the width and data type from the input signal. din can be a double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data Types: single | double | int8 | int16 | uint8 | uint16 | fixed point

Address that you write the data into when we is true. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | fixed point

When we is true, the RAM writes the data into the memory location that you specify.

Data Types: Boolean


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Output data from address, addr.


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Minimum bit width is 2, and maximum bit width is 29.

Programmatic Use

Block parameter: ram_size
Type: string scalar | character vector
Value: A minimum value of 2 and maximum value of 29
Default: '8'

Controls the output data, dout, during a write access. Specified as either:

  • New data—During a write, new data appears at the output port, dout.

  • Old data— During a write, old data appears at the output port, dout.

Programmatic Use

Block parameter: dout_type
Type: string scalar | character vector
Value: "New data" | "Old data"
Default: 'New data'


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HDL code generated for RAM blocks has:

  • A latency of one clock cycle for read data output.

  • No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2014a