Basic Coding Practices

HDL Coder™ conforms to the following naming conventions and basic coding guidelines and checks for modeling constructs that violate these rules. HDL Coder reports potential rule violations in the HDL coding standard report. To avoid these violations, see the rule recommendations.

1.A General Naming Conventions

1.A.A Design and Top-Level Naming Conventions

Rule / Severity	Message	Problem	Recommendations
1.A.A.1 Warning	`Verilog/SystemVerilog: Source file name should be same as the name of the module in the file.`	By default, HDL Coder generates code that has the same module and file name. If you use `BlackBox` architecture for your subsystem and generate code, the source names and file names can be different.	If you use `BlackBox` architecture for your subsystem, make sure that the source file name and module name are the same.
1.A.A.1 Warning	`VHDL: File names containing entities should have the extension .vhd or .vhdl.`	Source file name has to use certain recommended naming conventions and file extensions.	Use the VHDL file extension option in the HDL Workflow Advisor, or the `VHDLFileExtension` property from the command line.
1.A.A.2 Message	`Verilog/VHDL/SystemVerilog: Identifiers and names should follow recommended naming convention.`	A name in the design does not start with a letter or contains a character other than a number, letter, or underscore.	Update the names in your design so that they start with a letter of the alphabet (`a-z`, `A-Z`), and contain only alphanumeric characters (`a-z`, `A-Z`, `0-9`) and underscores (`_`).
1.A.A.3 Message	`Verilog/VHDL/SystemVerilog: Keywords in Verilog-HDL(IEEE1364), SystemVerilog(v3.1a), and keywords in VHDL(IEEE1076.X) must not be used.`	There are Verilog^®, SystemVerilog, or VHDL^® keywords within the names in your design.	Update the names in your design so that they do not contain Verilog, SystemVerilog, or VHDL keywords. You can disable this rule checking by using the `HDLKeywords` property of the HDL coding standard customization object.
1.A.A.3vb Message	`VHDL: Do not use standard VHDL names.`	HDL Coder does not use standard VHDL names.	No action required.
1.A.A.4 Error	`Verilog/VHDL/SystemVerilog: Do not use names starting with VDD, VSS, VCC, GND or VREF.`	A name or names in the design are not using the standard naming convention.	Update the names in your design so that they start with a letter of the alphabet (`a-z`, `A-Z`), and contain only alphanumeric characters (`a-z`, `A-Z`, `0-9`) and underscores (`_`).
1.A.A.5 Error	`Verilog/VHDL/SystemVerilog: Do not use case variants of name in the same scope.`	Two or more names in your design, within the same scope, are identical except for case. For example, the names `foo` and `Foo` cannot be in the same scope.	Update the names in your design so that no two names within the same scope differ only in case. You can disable this rule checking by using the `DetectDuplicateNamesCheck` property of the HDL coding standard customization object.
1.A.A.6 Warning	`Verilog/SystemVerilog: Primary port names or module names must follow recommended naming convention.`	HDL Coder generates code that complies with this rule for Verilog, SystemVerilog and VHDL.	No action required.
1.A.A.6 Warning	`VHDL: Component name should be same as its corresponding entity name.`		No action required.
1.A.A.9 Warning	`Verilog/VHDL/SystemVerilog: Top-level module/entity and port names should be less than or equal to 16 characters in length and not be mixed-case.`	A top-level module, entity, or port name in the generated code is longer than 16 characters, or uses letters with mixed case.	Update the indicated name in your design so that it is less than or equal to 16 characters long, and all letters are lowercase. all letters must be either all uppercase or all lowercase. You can customize this rule by using the `ModuleInstanceEntityNameLength` property of the HDL coding standard customization object.

1.A.B Module Naming Conventions

Rule / Severity Message Problem Recommendations

Rule / Severity	Message	Problem	Recommendations
1.A.B.1–1b Error	`Verilog/SystemVerilog: Module and Instance names should be between 2 and 32 characters in length. The instance names including hierarchy should be less than or equal to 128 characters in length.`	A module, instance, or entity name in the generated code is fewer than 2 characters or more than 32 characters in length.	Update the indicated name in your design so that it is from 2 through 32 characters in length. You can customize this rule by using the `ModuleInstanceEntityNameLength` property of the HDL coding standard customization object.
`VHDL: Entity names and instance names should be between 2 and 32 characters in length. The instance names including hierarchy should be less than or equal to 128 characters in length.`

1.A.B.1–1b
Error

Verilog/SystemVerilog: Module and Instance names should be between 2 and 32 characters in length. The instance names including hierarchy should be less than or equal to 128 characters in length.

A module, instance, or entity name in the generated code is fewer than 2 characters or more than 32 characters in length.

Update the indicated name in your design so that it is from 2 through 32 characters in length.

You can customize this rule by using the ModuleInstanceEntityNameLength property of the HDL coding standard customization object.

VHDL: Entity names and instance names should be between 2 and 32 characters in length. The instance names including hierarchy should be less than or equal to 128 characters in length.

1.A.C Signal Naming Conventions

Rule / Severity Message Problem Recommendations

Rule / Severity	Message	Problem	Recommendations
1.A.C.3 Error	`Verilog/SystemVerilog: Signal names, port names, parameter names, define names and function names should be between 2 and 40 characters in length.`	A signal, port, parameter, define, or function name in the generated code is fewer than 2 characters, or more than 40 characters in length.	Update function names or subsystem names in your design to be from 2 through 40 characters in length. You can customize this rule by using the `SignalPortParamNameLength` property of the HDL coding standard customization object.
`VHDL: Signal names, variable names, type names, label names, and function names should be between 2 and 40 characters in length.`

1.A.C.3
Error

Verilog/SystemVerilog: Signal names, port names, parameter names, define names and function names should be between 2 and 40 characters in length.

A signal, port, parameter, define, or function name in the generated code is fewer than 2 characters, or more than 40 characters in length.

Update function names or subsystem names in your design to be from 2 through 40 characters in length.

You can customize this rule by using the SignalPortParamNameLength property of the HDL coding standard customization object.

VHDL: Signal names, variable names, type names, label names, and function names should be between 2 and 40 characters in length.

1.A.D File, Package, and Parameter Naming Conventions

Rule / Severity	Message	Problem	Recommendations
1.A.D.1 Warning	`Verilog/SystemVerilog: Include files must have extensions that match ".h", ".vh",".inc", and ".h", ".inc", "ht", ".tsk" for testbench.`	The generated include files match these extensions for the testbench.	No action required.
1.A.D.1 Warning	`VHDL: Package file name should be followed by "pac.vhd".`	By default, the generated package file postfix is `_pkg`.	In the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings > General pane, specify the Package postfix to `_pac`.
1.A.D.4 Warning	`Verilog/SystemVerilog: Macros defined outside a module must not be used in the module.`	HDL Coder does not generate macros in the Verilog or SystemVerilog code, or redefine constants in the VHDL code.	No action required.
1.A.D.4 Warning	`VHDL: Constants should not be redefined.`		No action required.
1.A.D.9 Warning	`Verilog/SystemVerilog: Bit-width must be specified for parameters with more than 32 bits.`	HDL Coder does not specify a bit-width greater than 32 bits in the generated code.	No action required.
1.A.D.9 Warning	`VHDL: Generic must not be used at top-level module.`	If you use generics at top-level module or if you have mask parameters in your design and set the `MaskParameterAsGeneric` property, HDL Coder reports this violation.	If you have mask parameters in your design, set the `MaskParameterAsGeneric` to `off`.

1.A.E Register and Clock Naming Conventions

Rule / Severity Message Problem Recommendations

Rule / Severity	Message	Problem	Recommendations
1.A.E.2 Warning	`Verilog/VHDL/SystemVerilog: Clock, Reset, and Enable signals should follow recommended naming convention.`	The clock, reset, and enable signals are not using the recommended naming convention.	In the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings pane, using the clock input port, reset input port, and clock enable input port options, update the names for the clock, reset, and enable signals respectively. Follow these naming conventions: Clock signal names must be `clk` or `ck`. Clock enable signal names must be `en`. For 'active-high' reset, reset signal names must be `rst` or `reset`. For 'active-low' reset, reset signal names must be `rst`, `reset`, `rst_n`, `reset_n`, `rst_x`, or `reset_x`.

1.A.E.2
Warning

Verilog/VHDL/SystemVerilog: Clock, Reset, and Enable signals should follow recommended naming convention.

The clock, reset, and enable signals are not using the recommended naming convention.

In the Configuration Parameters dialog box, on the HDL Code Generation > Global Settings pane, using the clock input port, reset input port, and clock enable input port options, update the names for the clock, reset, and enable signals respectively. Follow these naming conventions:

Clock signal names must be clk or ck.
Clock enable signal names must be en.
For 'active-high' reset, reset signal names must be rst or reset.
For 'active-low' reset, reset signal names must be rst, reset, rst_n, reset_n, rst_x, or reset_x.

1.A.F Architecture Naming Conventions

Rule / Severity Message Problem Recommendations

Rule / Severity	Message	Problem	Recommendations
1.A.F.1 Warning	`VHDL: Architecture name must contain RTL.`	In the generated VHDL code, the architecture name does not contain RTL.	In HDL Code Generation > Global Settings > General tab, update the VHDL architecture name to use an architecture name that contains RTL.
1.A.F.4 Warning	`VHDL: An entity and its architecture must be described in the same file.`	By default, HDL Coder describes the entity and architecture of the VHDL code in the same file. If you set the `SplitEntityArch` property to `on`, the generated VHDL code describes the entity and architecture in separate files, so HDL Coder reports a warning.	Set `SplitEntityArch` to off so that HDL Coder describes the entity and architecture of the VHDL code in the same file.

1.A.F.1
Warning

VHDL: Architecture name must contain RTL.

In the generated VHDL code, the architecture name does not contain RTL.

In HDL Code Generation > Global Settings > General tab, update the VHDL architecture name to use an architecture name that contains RTL.

1.A.F.4
Warning

VHDL: An entity and its architecture must be described in the same file.

By default, HDL Coder describes the entity and architecture of the VHDL code in the same file.

If you set the SplitEntityArch property to on, the generated VHDL code describes the entity and architecture in separate files, so HDL Coder reports a warning.

Set SplitEntityArch to off so that HDL Coder describes the entity and architecture of the VHDL code in the same file.

1.B General Guidelines for Clocks and Resets

1.B.A Clock Constraints

Rule / Severity Message Problem Recommendations

Rule / Severity	Message	Problem	Recommendations
1.B.A.1 Message	`VHDL: Design should have only a single clock and use only one edge of the clock.`	Your design uses multiple edges of the clock or contains more than one clock signals. If you set the ClockInputs property to `multiple` or use `TriggerAsClock` to use the trigger signal for a triggered subsystem as clock, HDL Coder generates this message.	Update your design to use a single clock signal. In the HDL Code Generation > Global Settings panel, set Clock inputs to `Single`, and Clock edge to `Rising` or `Falling`.
1.B.A.2 Error	`Verilog/VHDL/SystemVerilog: Do not create an RS latch or flip-flop using primitive cells such as AND, OR.`	HDL Coder does not create latches, and complies with this rule.	No action required.
1.B.A.3 Error	`Verilog/VHDL/SystemVerilog: Remove combinational loops.`	HDL Coder does not create combinational loops.	No action required.

1.B.A.1
Message

VHDL: Design should have only a single clock and use only one edge of the clock.

Your design uses multiple edges of the clock or contains more than one clock signals.

If you set the ClockInputs property to multiple or use TriggerAsClock to use the trigger signal for a triggered subsystem as clock, HDL Coder generates this message.

Update your design to use a single clock signal. In the HDL Code Generation > Global Settings panel, set Clock inputs to Single, and Clock edge to Rising or Falling.

1.B.A.2
Error

Verilog/VHDL/SystemVerilog: Do not create an RS latch or flip-flop using primitive cells such as AND, OR.

HDL Coder does not create latches, and complies with this rule.

No action required.

1.B.A.3
Error

Verilog/VHDL/SystemVerilog: Remove combinational loops.

HDL Coder does not create combinational loops.

No action required.

1.C Guidelines for Initial Reset

1.C.A Flip-Flop Clock Constraints

Rule / Severity	Message	Problem	Recommendations
1.C.A.3 Warning	`Verilog/VHDL/SystemVerilog: Do not use asynchronous set/reset signals other than initial reset.`	HDL Coder does not use asynchronous reset signals as non-reset or synchronous reset signals.	No action required.
1.C.A.6 Error	`Verilog/VHDL/SystemVerilog: Signals must not be used as both asynchronous reset and synchronous reset.`	HDL Coder adds the reset control logic outside the DUT and does not generate both asynchronous reset and synchronous reset signals.	No action required.
1.C.A.7 Warning	`Verilog/VHDL/SystemVerilog: A flip-flop must not have both asynchronous set and asynchronous reset.`	HDL Coder does not generate code with both asynchronous set and reset signals.	No action required.

1.C.B Reset Conventions

Rule / Severity	Message	Problem	Recommendations
1.C.B.1a Message	`Verilog/VHDL/SystemVerilog: Asynchronous resets or sets must not be gated.`	HDL Coder does not gate asynchronous set or reset signals.	No action required.
1.C.B.1b Message	`Verilog/VHDL/SystemVerilog: Reset must be generated in separate module instantiated at top-level.`	The generated code complies with this rule, because the DUT does not contain reset instantiation.	No action required.
1.C.B.2 Warning	`Verilog/VHDL/SystemVerilog: Do not use signals other than initial reset for asynchronous reset input of flip-flop.`	HDL Coder uses only initial reset signals for asynchronous reset input of flip-flop.	No action required.

1.D Guidelines for Clocks

1.D.A Clock Packaging Constraints

Rule / Severity	Message	Problem	Recommendations
1.D.A.1 Warning	`Verilog/VHDL/SystemVerilog: Clock should be generated in separate module or entity instantiated at top-level.`	HDL Coder generates code that complies with this rule, because the DUT does not contain clock instantiation.	No action required.

1.D.C Clock Gating Constraints

Rule / Severity	Message	Problem	Recommendations
1.D.C.2–4 Message	`Verilog/VHDL/SystemVerilog: Do not use flip-flop outputs as clocks of other flip-flops and flip-flop clock signals as non-clock signals.`	HDL Coder does not use the output of flip-flops as clocks of other flip-flops, or flip-flop clock signals as nonclock signals.	No action required.
1.D.C.6 Message	`Verilog/VHDL/SystemVerilog: Do not use flip-flops with inverted edges.`	If your Simulink^® model uses a Triggered Subsystem block with rising and falling triggers and has `TriggerAsClock` enabled, HDL Coder violates this rule.	Disable `TriggerAsClock` or do not use Triggered Subsystem blocks with both rising and falling triggers in your Simulink model.

1.D.D Clock Hierarchy Constraints

Rule / Severity	Message	Problem	Recommendations
1.D.D.2 Message	`Verilog/SystemVerilog: One hierarchical level should have a single clock only.`	Your Simulink model uses multiple clock signals.	Update your design to use a single clock signal. In the HDL Code Generation > Global Settings panel, set Clock inputs to `Single`.

1.F Guidelines for Hierarchical Design

1.F.A Basic Block Size Guidelines

Rule / Severity	Message	Problem	Recommendations
1.F.A.4 Error	`Verilog/VHDL/SystemVerilog: Clock generation, reset generation, RAM, Setup/Hold ensure buffers, and I/O cells must be a module at top-level.`	HDL Coder generates separate modules for the DUT, RAM, timing controller, so that it complies with this rule.	No action required.