Terminate Unconnected Block Outputs and Usage of Commenting Blocks
You can follow these guidelines as recommended modeling practices such as making sure that block outputs are terminated and how you can comment out blocks for HDL code generation.
Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.
Terminate Unconnected Block Outputs
If you generate HDL code for a Subsystem that has unconnected output ports, HDL Coder™ generates an error. For output ports that are not connected to downstream logic, connect them to a Terminator block.
This model illustrates a
DUT0 Subsystem that has an unconnected output port
If you generate HDL code for this Subsystem, HDL Coder™ generates this error:
error in validation model generation: Failed to find source for outport 2 on 'DUT0' Please create a fully connected subsystem when generating the cosimulation model.
You can use the
addterms function to add Terminator blocks to unconnected ports in your model.
load_system('hdlcoder_terminateout') addterms('hdlcoder_terminateout') open_system('hdlcoder_terminateout')
Using Comment Out and Comment Through of Blocks
To exclude blocks in your model from simulation without physically removing the blocks from your model, use Comment Out or Comment Through. When you use Comment Out, the signals are terminated and grounded. When you use Comment Through, the signals are passed through.
When you generate HDL code, you can use this capability to exclude certain blocks such as blocks that are not supported for HDL code generation.
Open the model
The code generator supports blocks that are comment out when the output signals are unused. The generated code assigns a constant value of
0 to the signal at the output. The
Dut_CommentOut subsystem contains blocks that are commented out.
When you generate code, this VHDL® code generated for the
DUT_CommentOut subsystem indicates a constant zero value assigned to
ARCHITECTURE rtl OF Generated IS
-- Signals SIGNAL TmpGroundAtData_Type_DuplicateInport1_out1 : signed(15 DOWNTO 0); -- sfix16_En6
BEGIN -- Unsupported Block
TmpGroundAtData_Type_DuplicateInport1_out1 <= to_signed(16#0000#, 16);
Out1 <= std_logic_vector(TmpGroundAtData_Type_DuplicateInport1_out1);
The code generator supports blocks that are comment through. The generated code passes the input signal through to the output. The
Dut_CommentThrough subsystem contains blocks that are comment through.
When you generate code for
Dut_CommentThrough subsystem, the VHDL code shows
In1 passed through to
ARCHITECTURE rtl OF Generated_CommentThrough IS
BEGIN -- Unsupported Block
Out1 <= In1;