estimatePLLPhaseNoise
R2026bSyntax
Description
out = estimatePLLPhaseNoise(Block=gcb)
The function reads the parameters from the PLL block to build a phase-domain model. It then computes the phase noise contribution from each building block of the PLL including the VCO, reference, divider, charge pump, and loop filter resistors and capacitors, sums them in the linear power domain, converts the results to phase noise in dBc/Hz, and then plots the results against the offset frequency.
Note
You need a license to Control System Toolbox™ to use this functionality.
out = estimatePLLPhaseNoise(Block,Name=Value)
[
returns the PLL configuration and the estimated PLL phase noise.out,config] = estimatePLLPhaseNoise(Block,Name=Value)
out = estimatePLLPhaseNoise('',Architecture=Architecture,ReferenceFrequency=ReferenceFrequency,ChargePumpCurrent=ChargePumpCurrent,VCOSensitivity=VCOSensitivity,Name=Value)
Examples
Open the model simplePLL attached to this example as a supporting file. The model consists of an Integer N PLL with Single Modulus Prescaler block and a PLL Testbench block.
open_system('simplePLL.slx')
Double-click the Integer N PLL with Single Modulus Prescaler block to open the Block Parameters dialog box and verify these settings:
Check that the impairments are disabled in the PFD and Charge pump tabs.
In the Charge pump tab, the Output current is set to
2.7mA. The Deadband compensation and Input threshold parameters are kept at default values.
In the VCO tab, the VCO sensitivity is set to
20MHz/V. The free running frequency is set to2.78GHz, which is slightly lower than the target lock frequency. The phase noise frequency offset vector is set to[100e3 1e6 3e6 10e6]Hz. The phase noise level corresponding to these frequency offsets are set to[-108 -134 -145 -154]dBc/Hz.
Considering the reference input frequency to the PLL is 1.6 MHz, the Clock divider value and the Min clock divider value in the Prescaler tab is set to
.
In the Loop Filter tab, the Loop bandwidth is set to 160 kHz, 1/10th of the reference input frequency. The phase margin is kept at default 45 degrees. Filter component values are calculated automatically.
Estimate the phase noise contribution of individual building blocks.
out = estimatePLLPhaseNoise(Block='simplePLL/Integer N PLL with Single Modulus Prescaler')
--- PLL Phase Noise Contribution Summary ---
[not plotted] Reference - ReferencePhaseNoise not provided
[not plotted] Divider - DividerPhaseNoise not provided and UseDSMDividerNoise is false
[not plotted] PFD/CP - ChargePumpNoiseDensity is zero
[not plotted] R4 thermal - R4 is zero (not present)
[dominant] VCO - 100.0% of total integrated phase noise power
--------------------------------------------
out =
struct with fields:
FrequencyOffset: [502×1 double]
TotalPhaseNoise: [502×1 double]
VCOPhaseNoise: [502×1 double]
ReferencePhaseNoise: [502×1 double]
DividerPhaseNoise: [502×1 double]
ChargePumpPhaseNoise: [502×1 double]
R2PhaseNoise: [502×1 double]
R3PhaseNoise: [502×1 double]
R4PhaseNoise: [502×1 double]
OpenLoopGain: [1×1 tf]
ErrorTransferFunction: [1×1 tf]
ClosedLoopTransferFunction: [1×1 tf]
As you can see in this case, the only phase noise contribution is coming from the VCO.
Define the parameters for the PLL.
arch="integer-single"; % PLL architecture RF=10e6; % Reference frequency Icp=1e-3; % Charge pump current Kvco=100e6; % VCO sensitivity Rd=200; % Divider ratio CP_nf=0.0015; % Transistor-level noise factor CP_fc=100e3; % Charge pump flicker corner R_fc=50e3; % Resistor flicker corner VCO_pn=struct('f_Hz',[1e4 1e5 1e6 1e7], ... 'L_dBc_per_Hz',[-77 -108 -134 -154]); % VCO phase noise Target_pn=struct('f_Hz',[1e4 1e5 1e6 1e7], ... 'L_dBc_per_Hz',[-70 -100 -125 -145]); % Target phase noise
Estimate the phase noise contributions of individual components of the PLL.
out = estimatePLLPhaseNoise( ... Architecture=arch, ... ReferenceFrequency=RF, ... ChargePumpCurrent=Icp, ... VCOSensitivity=Kvco, ... DividerRatio=Rd, ... CPNoiseFactor=CP_nf, ... ChargePumpFlickerCorner=CP_fc, ... ResistorFlickerCorner=R_fc, ... R2=1330, C1=1.31e-11, C2=1.44e-10, ... R3=17000, C3=9.41e-13, ... VCOPhaseNoise=VCO_pn, ... TargetPhaseNoise=Target_pn)
--- PLL Phase Noise Contribution Summary --- [not plotted] Reference - ReferencePhaseNoise not provided [not plotted] Divider - DividerPhaseNoise not provided and UseDSMDividerNoise is false [not plotted] R4 thermal - R4 is zero (not present) [dominant] R3 thermal - 89.5% of total integrated phase noise power --------------------------------------------
out = struct with fields:
FrequencyOffset: [502×1 double]
TotalPhaseNoise: [502×1 double]
VCOPhaseNoise: [502×1 double]
ReferencePhaseNoise: [502×1 double]
DividerPhaseNoise: [502×1 double]
ChargePumpPhaseNoise: [502×1 double]
R2PhaseNoise: [502×1 double]
R3PhaseNoise: [502×1 double]
R4PhaseNoise: [502×1 double]
OpenLoopGain: [1×1 tf]
ErrorTransferFunction: [1×1 tf]
ClosedLoopTransferFunction: [1×1 tf]
TargetFrequencyOffset: [4×1 double]
TargetPhaseNoiseLevel: [4×1 double]
TargetDelta: [4×1 double]
Name-Value Arguments
Output Arguments
More About
Tips
If you are using a PLL block in a Simulink model, you can override any block parameter by specifying the corresponding name-value argument. For example,
estimatePLLPhaseNoise(Block=gcb, ChargePumpCurrent=2e-3)uses the loop filter and VCO settings from the block but overrides the charge pump current to 2 mA. This allows you to quickly estimate the effect of certain parameters without changing the model.You can use the returned transfer function objects further analyses, such as checking the gain and phase margins (
margin(out.OpenLoopGain)), verifying loop bandwidth (bandwidth(out.ClosedLoopTransferFunction)), and visualizing VCO noise shaping (bode(out.ErrorTransferFunction)).For quick sanity checks, verify that the loop bandwidth matches your design specifications and that the phase margin is above 45°.
Version History
Introduced in R2026b
