The code generator does not explicitly group primitive blocks that constitute a
nonatomic masked subsystem block in the generated code. This flexibility allows for
more efficient code generation. In certain cases, you can achieve grouping by
configuring the masked subsystem block to execute as an atomic unit by selecting the
Treat as atomic unit option.
HDL Coder™ provides additional configuration options that affect HDL
implementation and synthesized logic.
HDL ArchitectureThis block has one default HDL architecture.
HDL Block PropertiesConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
0 . For more details, see ConstrainedOutputPipeline (HDL Coder).
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InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0 . For more details, see InputPipeline (HDL Coder).
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0 . For more details, see OutputPipeline (HDL Coder).
|