EtherCAT Distributed Clock Algorithm

An EtherCAT^® network consists of a main device node (the target computer) connected to an arbitrary number of subordinate device nodes (devices). Each node contains a clock that controls its internal operation. When you enable distributed clocks in the ENI file by using the configurator program, EtherCAT designates one clock in the network as the reference clock. The EtherCAT distributed clock (DC) algorithm then synchronizes the operation of multiple network nodes to the reference clock.

The DC algorithm operates in two phases. In phase 1, the algorithm aligns the clocks of DC-enabled network nodes other than the main device node with the clock of the first DC-enabled subordinate device node. In phase 2, the algorithm aligns the remaining unaligned clock with the reference clock.

Main Device Shift Mode

In main device shift mode, the reference clock is the clock of the first DC-enabled subordinate device in the network.

In phase 1, the algorithm shifts the sample time of the network nodes to align with the clock of the first subordinate device node. In that process, the EtherCAT Init block output value NetworkToSubDeviceClkDiff decreases to near zero.

In phase 2, the algorithm shifts the sample time of the main device stack running on the target computer to align with the first subordinate device node clock. In that process, the EtherCAT Init block output value MdeviceToNetworkClkDiff decreases to near zero. If there are no DC enabled devices, both values are zero.

Bus Shift Mode

In bus shift mode, the reference clock is the clock of the main device stack running on the target computer.

In phase 1, the algorithm shifts the sample time of the DC-enabled network nodes to align with the clock of the first DC-enabled subordinate device node. In that process, the value NetworkToSubDeviceClkDiff decreases to near zero.

In phase 2, the algorithm shifts the sample time of the first DC-enabled subordinate device node to align with the clock of the main device stack. In that process, the value MdeviceToNetworkClkDiff decreases to near zero. The algorithm shifts the sample time of the other network nodes to stay aligned with the first subordinate device node clock. In that process, the value of NetworkToSubDeviceClkDiff can first increase, then decrease to near zero.

Limitations

To include EtherCAT distributed clocks when PTP is enabled for the model, use EtherCAT bus shift mode.