Assess logical expression and automatically log result
verify( evaluates a scalar logical
returns the specified error message for the failed
verify statement. If
you run the test in the Test Manager, the error message appears in the simulation log. If
you run the test outside the Test Manager, the message appears in the Diagnostic Viewer. To
format the error message, you can use any
sprintf format, except strings and chars in Stateflow® charts.
In a real-time environment,
verify statement failures do not
produce warnings. However, if you run a real-time test case in the Test Manager, the
failures are shown in the Verify Statements section of the test
case results. You can also access information about the
identifier as a label for the test results. The
identifier is used as the signal label in the Test Manager. If you
run the test outside the Test Manager, the label appears in the Simulation Data Inspector
or, for a failure, in the Diagnostic Viewer. The identifier is a string that has at least
two colon-separated MATLAB® identifiers.
Verify a Logical Expression
verify(x > y && z > 10)
Specify Error Message Text for
verify statement fails, it returns an error message that
lists the values of
verify(x > y && z > 10,'x, y, and z are %d,%d,%d',x,y,z)
Specify a Label for
The result of this
verify statement is prefaced by the label,
TestReq1:bothGreater and, if the test fails, the error
verify(x > y && z > 10,'TestReq1:bothGreater',... 'x, y, and z are %d,%d,%d',x,y,z)
Using verify in a Stateflow Chart
The second step in the Scenario1 state of this Stateflow chart verifies that the target equals 60.
You can use
verifystatements in Test Sequence and Test Assessment blocks and in Stateflow charts. A Stateflow license is required to use a chart.
verifystatements in charts are supported in the same locations, execution modes, and for the same code generation targets as the Test Sequence block.
You cannot use
Test Sequence blocks that use continuous-time updating. Test Sequence block data can depend on factors such as the solver step time. Continuous-time updating can cause differences in when block data and
verifystatements update, which can lead to unexpected
verifystatement results. If your model uses continuous time and you use
verifystatements in a Test Sequence or Test Assessment block, consider explicitly setting a discrete block sample time.
Moore, Mealy, Discrete Event, or continuous charts
Charts that use C as the action language
Bind actions in a chart
Transition or condition actions in a chart
MATLAB functions, graphical functions, or truth tables in a chart
MATLAB Function or Truth Table blocks
Rapid Accelerator mode simulations
Code generation targets other than Simulink® Real-Time™ and HDL Verifier™
Standalone Stateflow charts
If you use parallel test execution to run your tests, then you cannot use the Highlight in Model button for in the Test Manager to
You cannot use
verifyas a condition immediately after
whenin a When decomposition because
verifystatements do not produce output. You can, however, use
verifystatements as actions in When decomposition steps. See Assess a Model by Using When Decomposition.
When comparing floating-point data in
verifystatements, consider the precision limitations associated with floating-point numbers. If you need to use floating-point data, define a tolerance for the verification. For example, instead of
verify(x == 5), verify
xwithin a tolerance of 0.001:For more information, see Floating-Point Numbers.
verify(abs(x-5) < 0.001)