Last write transfer latency (clocks)

Delay in clock cycles between the end of a memory transfer and the end of a write transaction

Model Configuration Pane: Target hardware resources / FPGA design (PS mem controllers)

Description

Specify the delay in clock cycles between the end of a memory transfer and the end of a write transaction.

To set this value, measure the clock cycles between the end of the burst and the completion of the transaction on your board. For instructions for extracting this information from a hardware execution, see Configuring and Querying the AXI Interconnect Monitor.

Settings

5 (default)

Default: 5

Programmatic Use

Parameter:

Type:

Values: 5

Default: 5

Version History

Introduced in R2019a