Chroma Resampler

Downsample or upsample chrominance component

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Libraries:
Vision HDL Toolbox / Conversions

Description

The Chroma Resampler block downsamples or upsamples a pixel stream.

• Downsampling reduces bandwidth and storage requirements in a video system by combining pixel chrominance components over multiple pixels. You can specify a filter to prevent aliasing by selecting the default filter or by entering coefficients.

• Upsampling restores a signal to its original rate. To calculate the extra sample, you can use interpolation or replication.

The block accepts luma and chrominance components. The block does not modify the luma component, and applies delay to align it with the resampled chrominance outputs. The rate of the output luma component is the same as the rate of the input.

Examples

Convert RGB Image to YCbCr 4:2:2 Color Space

Convert a pixel stream from R'G'B' color space to Y'CbCr 4:2:2 color space.

• Open Model

Ports

This block uses a streaming pixel interface with a pixelcontrol bus for frame control signals. This interface enables the block to operate independently of image size and format. All Vision HDL Toolbox™ blocks use the same streaming interface. The block accepts and returns a scalar pixel value and a bus that contains five control signals. The control signals indicate the validity of each pixel and its location in the frame. To convert a frame (pixel matrix) into a serial pixel stream and control signals, use the Frame To Pixels block. For a full description of the interface, see Streaming Pixel Interface.

Input

pixel — Pixel in Y'CbCr color space

vector of three values

Pixel in Y'CbCr color space, specified as a vector of three values. Integer and fixed-point data types must be between 8 and 16 bits.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: single | double | uint8 | uint16 | fixed point

ctrl — Control signals associated with pixel stream

pixelcontrol bus

The pixelcontrol bus contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

Data Types: bus

Output

pixel — Pixel in Y'CbCr color space

vector of three values

Pixel in Y'CbCr color space, returned as a vector of three values. The data type of the output pixels is the same as the data type of the input pixels.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: single | double | uint8 | uint16 | fixed point

ctrl — Control signals associated with pixel stream

pixelcontrol bus

The pixelcontrol bus contains five signals. The signals describe the validity of the pixel and its location in the frame. For more information, see Pixel Control Bus.

Data Types: bus

Parameters

Main

Resampling — Type of resampling

4:4:4 to 4:2:2 (default) | 4:2:2 to 4:4:4

If you select 4:4:4 to 4:2:2, the block performs a downsampling operation. If you select 4:2:2 to 4:4:4, the block performs an upsampling operation.

Antialiasing filter — Lowpass filter to follow downsample operation

Auto (default) | Property | None

If you select Auto, the block uses a built-in lowpass filter. If you select Property, the Horizontal filter coefficients parameter appears on the dialog box. If you select None, the block does not filter the input signal.

Dependencies

This parameter is visible when you set Resampling to 4:4:4 to 4:2:2.

Horizontal filter coefficients — Coefficients for the antialiasing filter

[0.2 0.6 0.2] (default) | vector

Coefficients for the antialiasing filter, specified as a vector.

Dependencies

This parameter is visible if you set Resampling to 4:4:4 to 4:2:2 and Antialiasing filter to Property.

Interpolation — Interpolation method for an upsample operation

Linear (default) | Pixel replication

If you select Linear, the block uses linear interpolation to calculate the missing values. If you select Pixel replication, the block repeats the chrominance values of the preceding pixel to create the missing pixel.

Dependencies

This parameter is visible if you set Resampling to 4:2:2 to 4:4:4.

Data Types

The parameters on this tab appear only when they are relevant. If you configure the block so that no filter coefficients are needed, or no rounding or overflow is possible, the irrelevant parameter is hidden.

Rounding mode — Rounding method for internal fixed-point calculations

Floor (default) | Ceiling | Convergent | Nearest | Round | Zero

Specify a rounding method for internal fixed-point calculations.

Saturate on integer overflow — Overflow action for internal fixed-point calculations

off (default) | on

When you clear this parameter, fixed-point and integer values wrap around to zero when the value overflows what is representable with that data type. When you select this parameter, the value saturates at the maximum representable value.

Filter coefficients — Data type for antialiasing filter coefficients

fixdt(1,16,15) (default) | data type expression

This parameter applies when you set Antialiasing filter to Auto or Property.

Tips

• When you use a block with an internal line buffer inside an Enabled Subsystem (Simulink), the enable signal pattern must maintain the timing of the pixel stream, including the minimum blanking intervals. If the enable pattern corrupts the timing of the pixel stream, you might see partial output frames, corrupted pixel stream control signals, or mismatches between Simulink^® and HDL simulation results. You may need to extend the blanking intervals to accommodate for cycles when the enable is low. For more information, see Configure Blanking Intervals.

Algorithms

The default antialiasing filter is a 29-tap lowpass filter that matches the default Chroma Resampling block in Computer Vision Toolbox™. In the frequency response of this filter, the passband, [–0.25 0.25], occupies half of the total bandwidth. This filter suppresses aliasing after 4:4:4 to 4:2:2 downsampling.

Whether you use the default filter or specify your own coefficients, the filter is implemented in HDL using a fully parallel architecture. To reduce the number of multipliers, HDL code generation takes advantage of symmetric, unity, or zero-value coefficients.

The block pads the edge of the image with symmetric pixel values. See Edge Padding. Also, if the frame is an odd number of pixels wide, the block symmetrically pads the line. This accommodation makes the block more resilient to video timing variation.

Latency

The latency is the number of cycles between the first valid input pixel and the first valid output pixel. When you use an antialiasing filter, the latency depends on the size and value of the filter coefficients. The FIR delay can be less than the number of coefficients because the block optimizes out duplicate or zero-value coefficients.

Block Configuration	Latency
Downsample (4:4:4 to 4:2:2); no filter	3
Downsample (4:4:4 to 4:2:2); with filter	4+(N/2)+FIR delay, where N = number of filter coefficients
Upsample (4:2:2 to 4:4:4); replication	3
Upsample (4:2:2 to 4:4:4); interpolation	5

For example, the latency for a downsample using the default filter is 30 cycles.

Note

When you use edge padding, use a horizontal blanking interval of at least twice the kernel width. This interval lets the block finish processing one line before it starts processing the next one, including adding padding pixels before and after the active pixels in the line.

The horizontal blanking interval is equal to TotalPixelsPerLine – ActivePixelsPerLine or, equivalently, FrontPorch + BackPorch. Standard streaming video formats use a horizontal blanking interval of about 25% of the frame width. This interval is much larger than the filters applied to each frame.

The horizontal blanking interval must also meet these minimums:

• If the kernel size is less than 4, and you use edge padding, the total porch must be at least 8 pixels.

• When you disable edge padding, the horizontal blanking interval must be at least 12 cycles and is independent of the kernel size.

• The BackPorch must be at least 6 pixels. This parameter is the number of inactive pixels before the first valid pixel in a frame.

For more information, see Configure Blanking Intervals.

Performance

This table shows the resource use after synthesis of the block for Xilinx^® Zynq^®-7000 SoC ZC706 Evaluation Kit with single-pixel uint8 input and the default parameter settings. The design achieves a clock frequency of 371 MHz.

Resource	Usage
Slice LUTs	1225
Slice Registers	2656
DSP48	30
Block RAM	0

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2015a