APP Decoder

Decode convolutionally-coded LLR values using MAP algorithm

Since R2021b

• 

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The APP Decoder block decodes convolutionally-coded log-likelihood ratio (LLR) values using the maximum a-posteriori probability (MAP) decoding algorithm. The block accepts coded and uncoded LLR values and a samplecontrol bus, decodes the coded LLR values, and outputs the updated versions of the coded and uncoded LLR values and samplecontrol bus.

The block supports two decoding algorithms: Max Log MAP (max) and Log MAP (max*). You can select the algorithm by setting the Algorithm parameter. The block supports terminated and truncated modes and these decoding rates: 1/2, 1/3, 1/4, 1/5, 1/6, and 1/7. The block provides an architecture suitable for HDL code generation and hardware deployment.

The block supports decoding of serial and parallel concatenated codes. Using this block, you can build turbo decoders, custom decoders for concatenated codes, and product codes for iterative decoding.

Examples

Decode Convolutionally-Coded LLR Values Using APP Decoder

Decode convolutionally-coded LLR values using APP Decoder block.

• Open Script

Parallel Concatenation Using APP Decoder

Decode parallel concatenated convolution codes using APP Decoder block.

• Open Script

Ports

Input

LLRc — Coded LLR values

real-valued column vector

Coded LLR values, specified as a real-valued column vector of size N-by-1, where N is the decoding rate in the range from 2 to 7.

The input vector size depends on the code rate of the block. The block derives the code rate from the code generator polynomial value specified in the block mask. The block supports these code rates: 1/2, 1/3, 1/4, 1/5, 1/6, or 1/7.

double and single data types are supported for simulation, but not for HDL code generation. For HDL code generation, the block supports fixdt(1,WL,FL) data type and the input word length (WL) must be in the range from 4 to 16.

Data Types: single | double | int8 | int16 | signed fixed point

LLRu — Uncoded LLR values

real-valued scalar

Uncoded LLR values, specified as a real-valued scalar.

double and single data types are supported for simulation, but not for HDL code generation. For HDL code generation, the block supports fixdt(1,WL,FL) data type and the input word length (WL) must be in the range from 4 to 16.

Data Types: single | double | int8 | int16 | signed fixed point

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the input frame

• end — Indicates the end of the input frame

• valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

Output

LLRu — Uncoded LLR values

real-valued scalar

Uncoded LLR values, returned as a real-valued scalar. The output data type is the same as the input data type.

For inputs of fixed point data type, the output word length increases by floor(log₂(N)) + floor(log₂(K – 1)) + 2 bits. N is the code rate, and K is the constraint length of the block.

Data Types: single | double | int8 | int16 | fixed point

LLRc — Coded LLR values

real-valued column vector

Coded LLR values, returned as a real-valued column vector of size N-by-1. The output data type is the same as the input data type.

For fixed point inputs, the output word length increases by floor(log₂(N)) + floor(log₂(K – 1)) + 2 bits, where N is the code rate and K is the constraint length of the block.

Data Types: single | double | int8 | int16 | fixed point

ctrl — Control signals accompanying sample stream

samplecontrol bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

• start — Indicates the start of the output frame

• end — Indicates the end of the output frame

• valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

nextFrame — Block ready indicator

Boolean scalar

Block ready indicator, returned as a Boolean scalar.

The block sets this signal to 1 (true) when the block is ready to accept the start of the next frame. If the block receives an input ctrl.start signal while nextFrame is 0 (false), the block discards the frame in progress and begins processing the new data.

Data Types: Boolean

Parameters

Code generator — Code generator polynomial

[171,133] (default) | row vector of 2 to 7 elements

Specify a 1-by-n vector of octal values, where n is the length of the polynomial. The block accepts polynomials from 2 to 7 elements long.

The block derives the constraint length and code rate based on the specified code generator polynomial. Specify the code generator polynomial in such a way that the constraint length is in the range from 3 to 9 and the code rates are 1/2, 1/3, 1/4, 1/5, 1/6, or 1/7.

For more information on how to specify a code generator polynomial for decoding blocks, see Trellis Description of a Convolutional Code.

Feedback connection — Code generator polynomial

171 (default) | octal value

Since R2023b

Specify a scalar octal value with reference to the code generator value. If you specify 0 or [], the block performs decoding without feedback.

Termination method — End of frame behavior

Truncated (default) | Terminated

Select the termination method to specify the end of the frame behavior.

• Truncated — The block resets the state metrics after each frame, starts at the all-zeros state, and ends with the non-all-zeros state. The input ctrl bus qualifies the input samples and marks the frame boundaries.

• Terminated — The block resets the state metrics after each frame and starts and ends in the all-zeros state. The input ctrl bus qualifies the input samples and marks the frame boundaries.

Algorithm — Decoding algorithm type

Max Log MAP (max) (default) | Log MAP (max*)

Select the type of decoding algorithm.

• Max Log MAP (max) — Max log MAP approximation

• Log MAP (max*) — Log MAP approximation

For more information about these algorithms, see [1].

Window length — Window on which MAP algorithm is to be performed

64 (default) | integer in the range 3 to 128

Window on which the MAP algorithm is to be performed, specified as an integer in the range from 3 to 128. This integer represents the window length.

For better block performance results, the recommended window length is at least five times the constraint length.

Disable LLRc output port — Option to disable LLRc output port

off (default) | on

Select this parameter to disable the output port LLRc from the block. Clear this parameter to enable the output port LLRc on the block.

Algorithms

To perform MAP decoding, the block uses the Bahl, Cocke, Jalinek, and Raviv (BCJR) algorithm. The block implements MAP decoding using the log MAP approximation or max log MAP approximation algorithm. You can select the algorithm using the Algorithm parameter. These algorithms implement a-posteriori probability (APP) decoding. The max log MAP approximation option uses max(a_i) as the approximation, while the log MAP approximation option uses max(a_i) plus a correction term given by $$\ln (1+\exp (-\left|a_{i-1}-a_i\right|))$$ [1].

Latency

The latency of the block varies with the constraint length and the specified window length. The latency of the block is equal to 2 x W + 2^{(K - 1)} + 4. W is the window length, K is the constraint length, and 4 is the number of fixed pipeline delays.

This figure shows a sample output and latency of the APP Decoder block for the default configuration. In this case, the Code generator parameter is set to [171 133], the Feedback connection parameter is set to 171, the Termination method parameter is set to Truncated, the Algorithm parameter is set to Max Log MAP (max), and the Window length parameter is set to 64. The latency of the block is 196 clock cycles.

Performance

The performance of the synthesized HDL code varies with the target and synthesis options. It also varies based on the input data type.

This table shows the resource and performance data synthesis results when you provide an input data type of fixdt(1,8,3), specify the Code generator parameter as [5 7], select the Termination method parameter as Truncated, select the Algorithm parameter as Max Log MAP (max), and set the Window length parameter to 64. The generated HDL is targeted to the AMD^® Zynq^®- 7000 ZC706 evaluation board. The design achieves a clock frequency of 280 MHz.

Resource	Number Used
LUTs	2830
Registers	1326
DSPs	0
Block RAMs	0

References

[1] Viterbi, A.J. “An Intuitive Justification and a Simplified Implementation of the MAP Decoder for Convolutional Codes.” IEEE Journal on Selected Areas in Communications 16, no. 2 (February 1998): 260–64. https://doi.org/10.1109/49.661114.

[2] Benedetto, S., D. Divsalar, G. Montorsi, and F. Pollara. “A Soft-Input Soft-Output APP Module for Iterative Decoding of Concatenated Codes.” IEEE Communications Letters 1, no. 1 (January 1997): 22–24. https://doi.org/10.1109/4234.552145.

[3] Benedetto, S., and G. Montorsi. “Performance of Continuous and Blockwise Decoded Turbo Codes.” IEEE Communications Letters 1, no. 3 (May 1997): 77–79. https://doi.org/10.1109/4234.585802.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2021b

R2023b: Support trellis feedback structure

The APP Decoder block now supports trellis feedback structure through a new parameter Feedback connection. This parameter supports a scalar value.