Deploy WLAN HDL Reference Applications on FPGAs and SoCs

This section contains the list of examples that show how to deploy WLAN Wireless HDL Toolbox™ reference applications on FPGAs and SoCs.

• WLAN Receiver Using Analog Devices AD9361/AD9364 (SoC Blockset): Deploy a WLAN HDL receiver system to retrieve the signal and data field information from a WLAN signal for the 20 MHz channel bandwidth.

• WLAN Receiver Using AMD RFSoC Device (SoC Blockset): Deploy a WLAN transmit and receive algorithm.

These examples reuse the WLAN Simulink® models to generate HDL for the FPGA logic. They use hardware-software co-design modeling techniques and hardware support packages to add all the software modeling and interfacing required to implement the algorithm in real-time on hardware.

Related Topics

• HDL Implementation of WLAN Receiver
• WLAN HDL Frame Detection and Signal Recovery
• WLAN HDL Time and Frequency Synchronization