Dirty Model Refs with no change

I'm working in simulink model which has many model references. Some of the model references claim to have interface changes every time that the diagram has been updated. Some of them do not. When I do a model comparision the Mappings data claims to be updated.

the Mappings compare looks like this

If I open the top level model containing the model reference and update the diagram and save the model then close the models, re-open them again, the model reference wants to be saved again after a diagram update. Other model references contained inside the top level model don't asked to be saved and have less defined I/O ie some inherited stuff on their interfaces. I have defined all of the I/O as non-virtual buses, all datatypes on the inports and all sizes. All model refs share the same reference config. (the ones with the issue, the ones without) . There are no callbacks in the model properties.

How can I tell what is causing this to change every time the diagram is updated?

This is an issue because with source control its up to the developers to be careful to not commit these artificial changes. If there are not careful then annoying conflicts get generated all the time.

[Brent Jarvis]

I tried turning on callback tracing and the model ref that requires to be saved does not output a callback in the command window.

[Divyanshu]

Hi Brent,

I tried to reproduce the issue with the description provided with a basic 2-layer model. But I was not able to reproduce it. Can you share the model and some reproduction steps? It would be easier to track the issue.

[Arkadi Bahnmann]

We have the same issue in our project with Matlab 21b. It seems to be the combination of referenced models with bus element in ports. In Matlab 24b this problem seems to be solved. But we need a fix for 21b