I have an error regarding a data size mismatch in my DAC PL-DDR4 Transmit HDL code generation.

I am simply trying to create program my ZCU216 with the bitstream generated from the DAC PL-DDR4 example (found here: https://www.mathworks.com/help/hdlcoder/ug/hdl-dac-PL-DDR4-transmit.html). I copied all the project files, followed the HDL workflow, and generated a bitstream.

The script gs_waveformWriteDAC_DDR4_interface.m programs the bitstream and creates the FPGA object just fine. However, when the AXI4 Stream Interface is initiliazed in gs_waveformWriteDAC_DDR4_setup.m, the following error is generated:

Error using matlabshared.libiio.base/cstatusid

Data size mismatch.

This makes me think that the warning that appears upon opening the workflow advisor could be the issue "Current reference design requires the TDATA port width of the interface AXI4-Stream DMA Master to be 64 bits. It cannot fit model port "DMA_S2MM_Data" with bit-width 128". However, in step 1.2 of the workflow advisor, I made sure to set the AXI4-Stream DMA data width to 128 bits, which I thought would resolve the issue.

I'm not able to find this specific error online so I assume this problem is somewhat niche. I'm more than happy to elaborate any part of the setup that is not clear. Any suggestions are appreciated.