A question about the block named pixel to frame in simulink

Does the pixel to frame block make the algorithm which is based on frame run in the FPGA?Or it just for verifying the validity of image processing algorithm in FPGA.Thanks

Answer 1

[Bharath Venkataraman]

The Frame To Pixel and Pixel To Frame blocks allow you to convert to/from a streaming pixel interface. They do not generate HDL code for an FPGA implementation. The rest of the design will require a streaming pixel input.

You can however run the HDL with FPGA-in-the-Loop and feed it a frame of data using the FIL versions of the Frame To Pixel and Pixel to Frame blocks. The FIL block automatically adds in code to stream the frame of data in to the HDL code in the FPGA one pixel at a time and collects the pixel output into a frame at a time back into Simulink.

[Liclin]

So，most of algorithm can't run in the FPGA ? By the way,the FIL block I doesn't find in simulink block(matlab R2015a)

[Bharath Venkataraman]

The algorithm (say, 2-D Filter, Median Filter etc.) do run on the FPGA. The interface block converting from a frame of data to pixels is only for simulation.

The FIL blocks for Vision HDL Toolbox are shipped in the visionhdlio library.