Can I perform FPGA in the Loop with SysGen for DSP without HDL Coder and Verifier ?
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Yoni Levy on 9 Jun 2017
Commented: Yoni Levy on 14 Jun 2017
For my internship I have to implement FPGA in the Loop in Matlab. I have a licence for System Generator for DSP but it's not possible to have a license for HDL Coder or HDL Verifier. If I have already my VHDL code, it's possible to perform FIL with only SysGen for DSP ?
Thank you in advance
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