how to handle simulink output in which xilinx block sets with latency are used?

Hi everybody. I have a project implemented by Simulink, in which data (for example, 1000 samples) are injected into the model using the “From Workspace” block, and then, some processes are done on the data and return back to the workspace using the “To Workspace” block. This model is executed in software form and latency is not important and handled by the Matlab and Simulink (sample time sets to be 1). But now, I have to replace the Simulink blocks by the system generator blocks (hardware implementation), where some blocks (like Divider block) have several clock cycle delays (latency). The “From Workspace” block injects data into the model for each clock cycle (sample unit time) and the output of the model should be prepared at the same time. If all blocks of my model are combinational (with latency equal to 0) I don’t have any problem. But my challenge (problem) is around some blocks like Divider block (with several latency), because for example, when first data is injected into the model, the output is not prepared at the same time (not software model), and by injecting the second data in second clock cycle, the calculation would be wrong. Now, I don’t know how to handle the sample time in the model. Could anybody help me? I’m looking forward to hearing from anyone. Best Regards