Adjust the delay in the clock

Hi. I am designing delay control logic design in simulink. how can delay be controlled ? I attached a snap in which clock2 and clock3 has unit delay. I want to compensate that delay (in 4 steps) at every rising edge of clock4. for instance at 2nd edge of clock4 it should reduce clock2,clock3 delay by 0.25(25%) then, at 3rd edge of clock4 it adjusts 0.5(50%) and so on. so by the 4th step or 5th edge of clock4 the delay in clock2,clock3 become zero and it must align with clock1. how this logic can be designed ? Please help in this regard. Thanks in advance.